Synopsys XBC & XHC OTP NVM IP: SLP_A Architecture

The Synopsys XBC/XHC One Time Programmable (OTP) Non-Volatile Memory (NVM) IP, based on SLP_A architecture, employs a patented antiFuse bitcell operating on gate oxide breakdown as a programming mechanism. The IP can be manufactured without any additional masks or process steps, making it cost effective, reliable, and scalable. The bitcell is intrinsically secure making it virtually impossible to distinguish between programmed and unprogrammed locations upon visual inspection.

To serve a wide range of applications, The SLP_A architecture features optimized area for fast reads, with low active and standby power consumption. It provides an alternative to mask ROM, eFuses, and Flash memory in many applications.

The SLP_A architecture is designed for ease-of-integration into an SoC with multiple options and read modes to trade off area, speed, and power.

The OTP NVM IP memory array is delivered as a hard macro. An integrated power supply consisting of the high-voltage charge pump for programming and/or voltage regulator for reads is delivered as an optional hard macro.

Programming options include single and multi-bit. Single bit programming is supported with the embedded charge pump or an external supply. Multi-bit programming is facilitated by an external power supply. Only bits intended as 1s must be programmed. Unprogrammed bits remain 0s.

The SLP_A architecture is designed to minimize active and standby power consumption and uses only a 5.0V I/O device. The SLP_A architecture integrates various read operating modes and several test modes to simplify production testing and programming/verification.

The SLP_A architecture’s reliability is qualified to meet or exceed 10 years data retention per JEDEC/JESD standards for continuous operation at the maximum specified operating temperature. Characterization of skewed silicon material assures the specified performance parameters.

Synopsys XBC/XHC OTP NVM IP – SLP_A Architecture