Synopsys XBC OTP NVM IP: XPM Architecture
The Synopsys XBC One Time Programmable (OTP) Non-Volatile Memory (NVM) IP, based on the XPM architecture, employs a patented antiFuse bitcell operating on gate oxide breakdown as a programming mechanism. The IP can be manufactured without any additional masks or process steps, making it cost effective, reliable, and scalable. The bitcell is intrinsically secure, making it virtually impossible to distinguish between programmed and unprogrammed locations upon visual inspection.
To serve a wide range of applications, the XPM architecture features optimal area and performance, with low power requirements. The XPM architecture serves as an alternative to eFuse in several applications.
The XPM architecture is designed for ease-of-integration into an SoC and delivered as a single hard macro including voltage regulators and high voltage charge pump for programming.
No external voltages need to be supplied except for power.
In technology nodes ≤ 65nm, the XPM architecture’s bits are constructed with redundancy, i.e., with two OTP cells per bit, without compromising area optimization.
The production test flow is simplified and reduced to two essential tests and content programming.
Programming occurs at individual (single) bit granularity and only bits intended as 1s must be programmed. Unprogrammed bits remain 0s.
The XPM architecture’s reliability is qualified to meet or exceed 10 years data retention per JEDEC/JESD standards for continuous operation at the maximum specified operating temperature. Characterization of skewed silicon material assures the specified performance parameters.
- Memory capacity: 8 Kbits to128 Kbits
- Output data bus: 8 bits
- Dual power supply: VDD and VDDIO
- Embedded charge pump
- Factory and field programming
- Single bit programming
- Minimum data retention of 10 years
- Optimized for read access time
- Low power consumption
- Full redundancy in geometries ≤65nm (two OTP cells per logic bit)
- Highly secure