Synopsys IDE Security IP Module for CXL 3.x

The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general-purpose accelerators, memory expanders, and smart I/O devices requiring high performance, heterogeneous computing for data-intensive workloads.

The Synopsys CXL 3.x Integrity and Data Encryption (IDE) Security IP Module provides confidentiality, integrity, and replay protection for flow control units (FLITs) in the case of CXL.cache and CXL.mem protocols, and for FLITs and Transaction Layer Packets (TLP) in the case of CXL.io.

The Security Module implements the IDE specification as defined for CXL 3.x which also references PCI Express 6.x IDE specification for the CXL.io protocol. The Synopsys CXL 3.x IDE Security Module integrates seamlessly with the Synopsys CXL controllers to accelerate SoC integration.

The Synopsys CXL 3.x IDE Security Module provides full-duplex .cache/.mem/.io support with efficient encryption/decryption and authentication of FLITs and TLPs, based on optimized low latency AES-GCM cryptographic cores, that are specially developed for optimal area, performance, and latency implementations.

Learn about the broad portfolio of Security Solutions for Interfaces.


Synopsys IDE Secure Module for CXL 3.x Datasheet

 

Highlights
Products
Downloads and Documentation
  • Support for PCIe 6.0/6.1/6.2 IDE specification for CXL.io
  • Support for CXL 3.0 IDE specification for CXL.cache/mem
  • Support all required features of CXL 3.0 and CXL 3.1
  • High-performance AES-GCM-based packet encryption, decryption, authentication
  • FIPS 140-3 certification support
  • TDISP support for CXL.io
  • Seamless integration with Synopsys Controllers IP
    • FLIT interfacing for CXL.cache/mem
    • FLIT/TLP interfacing for CXL.io
    • Efficient sync/fail/status messaging
  • Customer configurable
    • Aligns with Synopsys CXL 3.x controller configuration options
    • Data bus widths: 128, 256, 512, 1024
    • Lanes: x2, x4, x8, x16
    • Support for all protocols CXL.cache/mem/io or only CXL.cache/mem
  • CXL.cache/mem
    • Containment & skid modes
    • Early MAC termination
  • Optimized for area, performance & latency
  • PCRC calculation & validation
  • Efficient key control & refresh
  • Bypass mode
CXL 3.0 Integrity and Data Encryption Security ModuleSTARs Subscribe
Description: CXL 3.0 Integrity and Data Encryption Security Module
Name: dwc_cxl_3_ide_security_module
Version: 2.13a
ECCN: 5D002.b2/ENC
STARs: Open and/or Closed STARs
Product Type: DesignWare Cores
Documentation:
Toolsets: Qualified Toolsets
Download: dw_iip_DWC_cxl_ide
Product Code: H314-0