Zephyr RTOS for Synopsys ARC Processors

Zephyr RTOS for Synopsys ARC® processors (ARC Zephyr) offers all of the benefits of open-source software, including complete source code and a large, growing user community. ARC Zephyr allows software developers to leverage a small-footprint real-time kernel for use in resource-constrained embedded systems together, while scalable to larger systems with a full range of support for communications protocols and file systems. ARC Zephyr runs on up-to-date 32- and 64-bit ARC processors, including ARC EMx, HS3x, HS4x, HS5x, HS6x and VPX processor families. The latest version of ARC Zephyr is available from the official Zephyr Project repository at GitHub.

The following features of ARC processors are supported in ARC Zephyr:

• Closely-coupled memories (ICCM & DCCM)
• Hardware-assisted unaligned memory access
• Interrupts with multiple priority levels
• Hardware floating-point unit (FPU)
• Symmetric multiprocessing (SMP)
• Hardware-assisted stack-checking
• Hardware-assisted atomic operations
• DSP ISA, AGU and XY-memory extensions
• Memory protection unit (MPU)

More detailed information is available in the Zephyr Project documentation.

ARC Zephyr is tested with Zephyr’s extensive built-in test suite on up-to-date Synopsys hardware development platforms, as well as on Synopsys ARC nSIM and open source QEMU simulators.

Read the Zephyr blog post "Zephyr RTOS is the Core of Synopsys Silicon Lifecycle Management Solution" for an ARC Processor based reference example showcasing how Synopsys' Silicon Lifecycle Management (SLM) solution provides a comprehensive roadmap not only for reliability and performance, but also for efficiency, and sustainability throughout the entire lifecycle of semiconductor devices.