Low Power Flow P&R (Backend Flow)


To highlight the tools and procedures of MV processing, you will perform the following steps:

  • Examine the design and UPF used during design synthesis
  • Floorplan a design with multiple power domains, including power-switched blocks
  • Create voltage areas to provide the physical context of MV floorplanning
  • Set up constraints and synthesize (PNS) multiple power grids, associated with voltage areas
  • Complete a post-PNS analysis of the power grids
  • Explore power switch configuration requirements; place the switches
  • Connect all power connections to macro and standard cells
  • Setup MV constraints on optimizations, high fanout synthesis, and scan chain placement during place_opt
  • Perform voltage-area aware clock-tree synthesis
  • Use the classic router in the presence of voltage areas
  • Setup a feedthrough methodology allowing routes through voltage areas
  • Perform chip-finishing tasks required
  • Analyze power grids using PrimeRail:
    • Static and Dynamic IR drop
    • Generate current waveforms for MTCMOS switches
    • De-coupling capacitor requirements


At the end of this workshop, you should be able to perform the following high-level design objectives:

  • Input a synthesized design into a Milkyway database
  • Analyze power domains in the synthesized design
  • Create a non-hierarchical floorplan with multiple-voltage areas corresponding to the power-domains
  • Synthesize multiple power networks corresponding to power supplies defined by UPF
  • Explore the requirements for MTCMOS switches in the design; place and connect the switches
  • Analyze the power grids post-synthesis
  • Run the placement, CTS, and routing stages of the design
  • Deal with common yield and reliability issues
  • Perform detailed static and dynamic analysis on power grids

Audience Profile

CAD, Logic Design and/or Physical Design engineers who have a need to implement, analyze, and verify designs requiring the lowest possible power consumption using the Synopsys Eclypse Low-Power Flow.


To benefit the most from the material presented in this workshop, students need:

  • A basic working knowledge of Synopsys IC Compiler and/or PrimeRail tools.
  • Working knowledge of the other Synopsys tools used (list at the end of course description) in the workshop is desirable, but not required, to complete this workshop.
  • An awareness of the basics of low-power design techniques. The workshop teaches how to implement these techniques. For students who want more information on these techniques, see the LPMM (Low-Power Methodology Manual) available for download on SolvNet.

Course Outline

Day 1

  • Introduction
  • Lab UPF and overview
  • MV Design and Power Grid Planning (Lab)
  • Physical Implementation

Day 2

  • Physical Implementation (Lab)
  • Chip Finishing (Lab)
  • Dynamic Rail Analysis (Lab)
  • Customer Support

Synopsys Tools Used

  • IC Compiler 2008.09-SP2
  • PrimeTime-PX 2008.06-SP3
  • PrimeRail 2008.09