Cloud native EDA tools & pre-optimized hardware platforms
WeiHsun is a guest author and Deputy Manager, Core Methodology Department, at Global Unichip Corp.
In the rapidly evolving world of ASIC design, the shift from monolithic to 2.5D and 3D multi-die architectures represents a significant leap forward. This approach, which integrates multiple chiplets (also knowns as dies) into a single package, demands not only a new level of IC design innovation but also an increased complexity in coordination and integration. At the forefront of this technological revolution is Global Unichip Corp. (GUC), which has effectively harnessed the power of Synopsys’ 3DIC Compiler, a unified exploration-to-signoff platform, to streamline its chip design processes and reduce overall cycle time.
GUC recently presented their multi-die tape-outs at SNUG Silicon Valley 2024, which were made more efficient by Synopsys’ 3DIC Compiler through the implementation of die floorplanning and related bump assignments. 3DIC Compiler helped further check the physical and logical connectivity, sync up information from die to die quickly, and, ultimately, shorten chip design cycle timelines for GUC’s 2.5 and 3D CoWoS designs.
This distinction between 2.5D and 3D IC design approaches becomes critical in addressing the increasing demand for higher performance and more integrated systems. Each method comes with its unique set of challenges and benefits, tailored to specific application needs.
2.5D and 3D design typically involves using an interposer, such as Chip-on-Wafer-on-Substrate (CoWoS), which enables the connection of silicon dies to a substrate via microbumps and C4 bumps, along with Through-Silicon Vias (TSVs). This architecture supports heterogeneous integration and the assembly of chiplets to achieve high memory bandwidth. However, it also introduces several challenges:
Conversely, 3D design strategies, such as System on Integrated Chips (SoICs), involve stacking chips directly using hybrid bonding. This stacking method differs significantly from 2.5D design as it utilizes hybrid bonding, allowing for a smaller chip size, better yield, and productivity. Key challenges include:
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The choice between 2.5D and 3D design approaches depends largely on the specific application requirements, including size, performance, and integration complexity. The 3DIC Compiler from Synopsys provides a suite of tools in a unified platform that empowers GUC to handle various critical aspects of multi-die system design:
The 3DIC Compiler features listed above translate directly into time saving and optimization benefits that GUC directly experienced.
“GUC’s use of the Synopsys 3DIC Compiler platform has not only optimized its design and validation processes but also significantly accelerated its time to market for multi-die packages,” said WeiHsun Liao, Deputy Manager at GUC. “By automating routing, which led to 50% reduction in implementation time, and incorporating powerful signoff tools, GUC can focus more on innovation and productivity, rather than on addressing iterative design challenges.”
As the semiconductor industry progresses toward more sophisticated and integrated solutions, platforms like Synopsys’ 3DIC Compiler become indispensable in managing increased complexity and ensuring the success of next-generation multi-die packages. By addressing these challenges with 3DIC Compiler, GUC continues to lead in the creation of advanced multi-die packages, showcasing the potential of both 2.5D and 3D technologies in overcoming modern electronic design hurdles.
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