Boosting Chip Design & Verification with AI EDA Tools

Chip designers are finding a valuable ally in artificial intelligence (AI) as they balance demands for greater performance, the challenges of increasing design complexity, engineering resource constraints, and the ever-present need to meet stringent time-to-market targets. By deploying AI-driven chip design and verification, teams are freed from iterative work and can focus instead on product differentiation and power, performance, and area (PPA) enhancements.

What engineers will be able to extract from their chips is becoming increasingly important in our smart everything economy. We’re in a time when essentially every device is a smart device—capturing data and transporting it to very large environments where the data gets crunched, AI models are built, insights are derived, and data gets pushed back to the edge to enhance productivity and quality of life. These demands on our devices are pushing the semiconductor industry toward a trillion-dollar trajectory. At the same time, the engineering talent shortage is real. While investments such as the CHIPS and Science Act of 2022 will eventually help fill the talent pipeline, so too will AI.

As a testament to how AI is rapidly becoming mainstream in its application in electronic design automation (EDA) and transforming the semiconductor world, the award-winning Synopsys DSO.ai AI application for chip design has notched its first 100 production tapeouts. This marks a significant milestone in an industry where AI has been the talk of the town but is only starting to make serious inroads.

Synopsys DSO.ai searches design spaces autonomously to discover optimal PPA solutions, massively scaling the exploration of choices in chip design workflows and using reinforcement learning to automate many otherwise menial tasks. Everyone from new to seasoned engineers stand to benefit, as the solution is somewhat like having an expert engineer in a box. Some of our customers are using DSO.ai in the cloud, tapping into the flexibility, scalability, and elasticity that on-premises and public cloud vendors offer to accommodate massive workloads and drive productivity to new heights. We’ve seen some impressive results from these initial customer use cases: productivity boosts of more than 3x, power reductions of up to 15%, substantial die size reductions, and less use of overall resources.

Deepening Demand for Better Power, Performance, and Area

With the uncertainties in our current global economy, the semiconductor landscape has become even more competitive, driving up demands for even better PPA, cost advantages as well as faster time to market. As a result, design teams are under pressure to deliver chips with better specs than their competitors can achieve. At the same time, resource constraints mean that teams are striving to do more with the same or fewer resources. There are also many relatively new players in the chip design arena, as hyperscalers and verticals like automotive companies are now designing their own chips. AI can help fill in the resource and expertise gaps.

Not only can AI tackle the iterative legwork of chip design, it can also accelerate processes to help teams get to the finish line faster. Take verification as an example. A production chip may actually be in its third revision of the hardware because the verification cycle didn’t complete in time for tapeout. However, if AI can accelerate verification coverage so that engineers can generate a bug-free version of their chip with fewer iterations, they can save a substantial amount of time and money.

Simply put, AI augments what humans can do. Humans are great at coming up with unique ideas, but those ideas are typically at the system or architectural level. To implement these ideas, engineers need EDA tools. And to help speed up the implementation, Synopsys sees AI as a way forward. By integrating AI into our solutions and making their use as easy and seamless as possible, we can help engineers achieve their goals faster. With reduced design and verification cycles and effort, design teams can spend more of their time innovating on their core ideas.

Controlling Chip Design Costs and Supply Chain Vulnerabilities

Economic uncertainties are also weighing on design budgets. Because advanced nodes are getting more expensive, we’re seeing a stronger drive to squeeze out as much as possible on the PPA front. Foundries typically offer performance- and cost-optimized versions of their process technologies. Within these versions, there are still many variations to fine-tune to determine which configuration is optimal, triggering an explosion in the exploration space. This is where AI, with its substantial capacity for design space exploration, can make it faster and easier to decide on a process technology variation.

Some design teams are now adopting a multi-foundry strategy to mitigate the impact of supply chain vulnerabilities and to lower costs. Moving a design from one foundry to another can be quite resource-intensive, making this task ideal for AI. In fact, in the interest of cost optimization, we’re seeing designers of legacy devices, particularly those on small teams, turning to AI to achieve more stringent area targets.

As this year unfolds, we expect to see continued acceleration in the adoption of AI for chip design and verification. With multi-die systems becoming more prevalent—including for compute-intensive applications such as AI itself—there will be a greater need for tools that can take on the high volume of repetitive tasks required to optimize for PPA. We will also continue to invest in AI to provide a seamless experience for designers who need to enhance their productivity and accelerate their design and verification cycles with the resources they have.