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Formal Verification for Custom Digital Design
Synopsys ESP is an equivalence checker for full custom designs. It enables fast and reliable comparison of a Verilog reference design against a transistor-level SPICE netlist. It is ideally suited for a wide range of custom digital applications, including:
- Compiled and custom memories (i.e. CAM, SRAM, ROM, etc.)
- Datapath blocks
- Programmable Logic (FPGA)
- Standard cell and I/O libraries
Introduction to ESP for Custom Design Formal Verification
Learn how ESP can solve your custom digital verification challenges.
High Coverage Verification with ESP Symbolic Simulation
Learn how ESP’s powerful symbolic simulation technology can provide high functional verification coverage orders of magnitude faster than SPICE.
Functional Timing Accuracy with ESP Device Model
Learn how the ESP device model technology can deliver speed and functional timing accuracy.
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Nov 18, 2024
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