Industry First Verification IP for Arm AMBA DTI-G

Introduction to AMBA DTI

The Arm® AMBA® Distributed Translation Interface (DTI) protocols are used by implementations of Arm® System MMUv3 (SMMUv3) Architecture specifications, such as Arm MMUs.  Such MMU implementation consists of the following key components:

• Translation Control Unit (TCU)
• Translation Buffer Unit (TBU)
• PCI Express (PCIe) Root Port with Address Translation Services (ATS) support
• DTI interconnect that manages the communication across the above components

The DTI specification defines two protocols:

• DTI-TBU protocol: Defines communication between a TBU and a TCU
• DTI-ATS protocol: Defines communication between a PCIe root port and a TCU

Refer to Arm® AMBA® DTI Protocol Specification for more details on the above components and related details. The DTI specification was first published in Nov 2016 and has undergone several revisions ever since, introducing newer versions of TBU and TCU protocols to support evolving Arm SMMU architectures. 

AMBA DTI-G Updates Overview

Arm recently announced the availability of the next version of the Arm AMBA DTI Protocol Specification, DTI Issue G (DTI-G), that is built on top of the DTI-F specification.

Let us briefly look into the DTI-G specification updates for DTI-TBU and DTI-ATS protocols.

Updates to DTI-TBU Protocol:

• Protocol version: DTI-G supports protocol version DTI-TBUv4. Additional encoding is introduced to support this version.
• Device permission table (DPT) support: The Device Permission Table (DPT) and associated behaviour provide a mechanism to enforce the association between granules of physical address space and the memory footprint of virtual machines. This means the physical memory pages of a virtual machine can be protected from accesses from a malicious virtual machine when both virtual machines are required for DPT check.
• MPAM Part ID extension: Memory Partition and Performance Monitoring (MPAM) defines independent partition ID (PARTID) spaces for each Physical Address Space (PAS). DTI-G provides an option to extend the MPAM PARTID width from 9 bits to 12 bits.
• DCP and DRE permissions for bypass response: DTI-G provides provision to set the value of direct cache prefetch (DCP) and destructive reads (DRE) based on the bypass response type for DTI-TBUv4.

Updates to DTI-ATS Protocol:

• Protocol version: DTI-G supports protocol version DTI-ATSv4. Additional encoding is introduced to support this version.
• Translation token extension: The width of the translation token, which is used to limit the number of outstanding translation request, is extended from 8 bits to 12 bits. Subsequently the translation id field is also extended from 8 to 12 bits.

Synopsys AMBA DTI-G VIP

Synopsys VIP for DTI provides verification of design implementation based on all DTI specifications. With support for DTI-G, the Synopsys VIP provides an end-to-end verification solution and addresses design verification complexities through the following features:

• Support for protocol version 4.0 while maintaining backward compatibility for previous versions.
• Native System/Verilog UVM architecture which facilitates easy integration into simulation environments and speeds up the development of test benches.
• Performance analysis and comprehensive debug capabilities to check for functional correctness.
• In-built sequence collection, functional coverage model, and verification plans to expedite the verification process and ensure fast bring-up and achieve wholistic verification closure.
• Rich configurability options and built-in protocol checks to stay competitive in a market where protocol developments are already being adopted.

Conclusion

Synopsys is partnering with early customers and collaborators to enhance the standard architecture for their next-generation designs, incorporating new features now available with the latest specifications. 

Synopsys VIP is natively integrated with the Synopsys Verdi® Protocol Analyzer debug solution as well as Synopsys Verdi® Performance Analyzer. Running system-level payload on SoCs requires a faster hardware-based pre-silicon solution. Synopsys transactors, memory models, hybrid and virtual solutions based on Synopsys IP enable various verification and validation use-cases on the industry’s fastest verification hardware, Synopsys ZeBu® emulation and Synopsys HAPS® prototyping systems. 

More information on Synopsys AMBA® VIP and Test Suites is available at http://synopsys.com/vip