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So you want to conquer your next big chip design using an advanced node FinFET process? From high-performance computing to the mobile edge, where a web of AI- and ML-enabled interconnected things are serving up real-time answers on the fly, one thing is for certain: Getting your library characterization right will help you reach design signoff faster and reduce the possibility of a respin.
Advanced process 3D FinFET technology enables more transistors to be packed into less space than ever. In fact, TSMC anticipates that its next-generation 3nm N3 process will have up to 70% density gain and up to 15% speed improvement at the same power as the previous N5 generation. But in addition to this technology enabling the future, there are more prominent timing, noise, and power variations that come along with it. And with hundreds of process, voltage, and temperature (PVT) corners on tens of thousands of cores, the scale of that challenge is getting bigger all the time.
We are far from the days of simple lookup table (LUT)-based non-linear delay model/non-linear power model (NLDM/NLPM) modeling for library-cell timing, noise, and power management. So in this new era of complexity, how do you ensure rapid chip design success even while compute demand is rising and market windows are narrowing?
TSMC and Synopsys have recently collaborated to lower your barrier to entry on advanced process FinFET technologies. Together we are helping to ensure your design success with our latest library characterization innovations to meet the moment.
Optimize Your Chip Design Process on Advanced FinFET Nodes
A typical digital design flow goes like this: synthesis, auto place and route (APR), timing and power signoff, and electromigration/IR drop (EMIR) analysis. The standard cell libraries are deeply embedded throughout the first three phases of the design process. When all four phases are complete, then the design moves to physical verification.
The following key features for the TSMC N5, N4, N3 process nodes will help make this design journey a whole lot easier:
- Advanced design rule compliance: Advanced routing will automatically comply to all the routing rules. Cell libraries are power-performance-area (PPA) optimized.
- Liberty™ Variation Format (LVF) enablement: LVF is enabled for the non-Gaussian timing variations present in FinFET technology and the accuracy is verified by running traditional Monte Carlo simulations for more accurate timing analysis.
- M0/M1 routing: Achieves a tighter design with better speed.
- Routing layer optimization: Enables more compact loading through different layers of resistance.
- Via pillar insertion: Improves interconnect resistance, for a faster, more compact design.
- Self-heating and aging analysis: Integrates user-friendly analysis into the enhanced SPICE model for greater reliability.
While these features will help you smooth your path to a successful design outcome, your library data accuracy is at the center of it all—pivotal to modeling increased design complexity at advanced nodes.
Comprehensive Library Characterization with Signoff-Quality Libraries
TSMC and Synopsys have collaborated to help you achieve signoff-quality libraries with maximum characterization throughput on available compute resources for accurate, fast signoff. These optimized standard cell libraries, otherwise known as “Golden Reference” libraries, enable you to optimize your chip designs to conquer those timing, noise, and power variations at scale. The library characterization generates Liberty files for numerous cell types and conditions to confirm accuracy. And inside the libraries, you’ll find a wide variety of design views, including views for:
- Various downstream tools
- Pre-layout designs (simple views)
- Net lists
- A .gds for each cell layout
- Liberty files, containing timing delay, power, EM effects, and noise models
- Verilog views
8×8 delay tables and 5×5 constraint tables have the wide variety of input and load combinations that affect a cell’s performance. And LVF helps with accuracy on top of this. TSMC also offers various cell types like lever shifters, retention cells, synchronizers, single-bit and multiple-bit flip flops, and a lot more along with various PVT conditions and slew-load combinations.
Special features will help additionally streamline the design and production process. For example, the incremental characterization capability allows you to characterize new or problem cells on the fly, or recover from unexpected farm or network glitches
Get Comprehensive Library Characterization with the SiliconSmart Core Engine
In designing for TSMC advanced processes, you will prepare your design, including net lists, process models, and PVT conditions, and input it into a characterization tool. From there, Synopsys SiliconSmart® standard cell, I/O, and memory characterization tool will deliver the library characterizations as well as quality assurance that’s tuned to produce Synopsys PrimeTime® signoff-quality libraries.
Library characterizations in advanced nodes require speed and accuracy. The Synopsys SiliconSmart solution delivers both. As part of the Synopsys Digital Design Family, it uses reference SPICE engines for faster characterization of advanced Liberty models used by the Synopsys PrimeTime static timing analysis solution to account for effects in low-voltage FinFET processes that affect timing. TSMC has certified the Synopsys SiliconSmart solution for its N5, N4, and N3 nodes. This means that you can take advantage of these high-performing technologies while optimizing your performance and productivity—fast tracking your silicon production in highly competitive, leading-edge markets.
We know that great advances don’t happen in a box. The Synopsys-TSMC collaboration goes far beyond library characterization. Our longstanding relationship includes collaborations on various design flows and Synopsys IP optimized for TSMC’s latest process technologies. Working together, we aim to deliver best-in-class semiconductor solutions that you can trust to help you bring your next big idea to life.