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As we discussed in Part 1 of this three-part blog series, linting as a technology priority has evolved significantly over the years. Today, contemporary chip designs contain a wide variety of functional errors and design issues that can hamper a product’s quality, ranging from risky coding practices in register transfer level (RTL) design descriptions to complex hardware-software interaction bugs that show up only after design production.
To stay ahead of costly and time-consuming design reworks or respins, teams not only need smart linting tools to identify the maximum number of RTL issues upfront, but they also require a set of predefined, recommended basic and advanced linting checks to rely on in times of need. This very philosophy became the core foundation of our Synopsys GuideWare™ methodology, a comprehensive rule set we developed in-house for design teams to accelerate lint workflow bring-up and push their designs across the finish line on time, every time. Leading semiconductor companies widely adopting our guided rule sets are a testament to the methodology’s continued success.
In Part 2 of this linting series, we’ll delve into the multiple design challenges that led to the genesis of Synopsys GuideWare for automotive and aerospace applications, touch on design issues that can be identified earlier at the RTL level using Synopsys GuideWare—encapsulated within Synopsys VC SpyGlass Lint instead of causing unnecessary iterations during the synthesis or logic equivalency stage—and, lastly, highlight a few advanced issues that can be caught using Synopsys VC SpyGlass functional lint analysis.
Targeted Problems: Synopsys GuideWare Hitting the Nail on the Head
Let’s say you’re building a Star Wars Lego set. Think of the GuideWare methodology as the base Lego block that you need to use at the very start before you begin adding more to build the structure. From there, users have the freedom to customize which colored Lego block they choose next to enhance the base structure. Similarly, users of all skillsets can modify and build their own lint methodology on top of the recommended Synopsys GuideWare set, leveraging the industry’s most comprehensive knowledge base of design expertise and best practices to enable user-specified extensions.
By designing a trusted methodology, we finally have a thorough, step-by-step linting check process that customers can use as soon as the RTL code is written. This methodology documentation with rule sets becomes a critical framework for the team to enforce a consistent style throughout the design, all while accelerating runtime with multi-core design execution.
Different applications, such as automotive or aerospace, require specific linting because of their distinct design needs. For instance, designs targeting ISO 26262 for automotive applications need to ensure there is no logic congestion or large muxes inference or delays used in the design, which are not good practices. Automotive designers highly prefer a modular and reusable design methodology, and our GuideWare Lint Automotive helps meet this objective.
Similarly, designs having military or aerospace as an end-user application, typically aiming for DO-254 certification, need to make sure designs are more secure with respect to clock and reset inference and its end use. For example, buffered or gated clock usage is not recommended, and a clean and structured clock/reset tree is critical for a secure design. Design gaps such as floating pin, dead code, registers, and others could lead to serious hindrances to DO-254 compliance targets. Therefore, the GuideWare Lint methodology acts as a saving grace, helping designers get the design right in the first go. While Synopsys continues to develop predefined linting rule sets for assurance and automotive applications, it’s worth noting that users can leverage the existing rulesets for ISO 26262 and DO-254 in addition to existing GuideWare rule sets to address automotive and military application needs—a feat we do not take lightly.
By adopting a “shift left” identification approach, Synopsys VC Spyglass Lint leverages consistent language construct support with Synopsys Design Compiler® and Synopsys Formality solutions, as well as deploys reliable implementation of language constructs across these technologies. With Synopsys VC SpyGlass Lint, designers can identify complex verification issues during equivalence checking earlier at the RTL stage, reducing iterations over the downstream stages. Our methodology also provides dedicated rulesets to catch simulation-synthesis mismatches.
Beyond the Ordinary: Functional Lint Analysis
The goal of functional verification is to find the maximum set of problems as early in the development process as possible. Semantic and syntactic checks play a critical role in fixing strenuous portability challenges over time.
At Synopsys, we worked hard to leverage the depth and breadth of our linting expertise to go beyond traditional linting approaches to include functional linting checks. With Synopsys VC SpyGlass Lint, designers gain access to a unique push-button flow for smarter, faster, and deeper functional lint analysis. Users no longer need to provide complex constraints or be experts in formal verification; instead, they can rely on our seamless hybrid flow to accelerate RTL signoff. Synopsys VC SpyGlass leverages native Synopsys VC Formal™ technology, providing a comprehensive, easy-to-use, and low-noise method for solving RTL design issues, such as width mismatch and out of bound checks, thereby ensuring high-quality RTL with fewer but meaningful violations.
For instance, critical checks like DeadCode, used to identify unreachable RTL sections, and FSM LiveLock check for infinite wait within multiple states and cannot be identified by traditional linting technologies; however they can be addressed using Synopsys VC SpyGlass Functional Lint technology. Easy debug features, such as the waveform viewer and schematic viewer with detailed annotations further reduce design verification time. Additionally, the code complexity dashboard gives management teams an estimate regarding the complexity of the RTL. These unique features provide designers with much-needed visibility of potential errors before they become severe problems in the downstream phases.
Smarter, Faster, Deeper RTL Signoff: The Next Generation of Lint Technology
Undeniably, linting has made life easier for designers to deliver code that is more robust and better suited for downstream verification and implementation. At Synopsys, we are proud to see how our unwavering commitment to helping customers find bugs and other design errors earlier has pioneered the way forward for linting. Synopsys VC SpyGlass, the next generation RTL signoff platform, which includes CDC, RDC, and Lint technologies, has already seen wide adoption and helped companies like STMicroelectronics achieve up to 4x faster CDC/RDC verification with VC SpyGlass technology.
Today, Synopsys GuideWare methodology and functional lint flow leveraging native Synopsys VC Formal technologies within VC SpyGlass Lint have become a fundamental design methodology at industry-leading ASIC/SoC companies and are already widely adopted by leading semiconductor companies. New customers who have just started their chip design process opt for the VC SpyGlass technology as their first choice, gain a quick jumpstart on the technology, and essentially demand VC SpyGlass Lint be part of their RTL flow.
Our experience with the Top 20 semiconductor customers has helped us match latest industry standards and develop comprehensive linting tools for RTL signoff, all while offering an unmatched depth of design coverage and breadth of various RTL scenarios and coding styles.
Stay tuned for the final part of this series where we will dissect how the integration of machine learning and RCA capabilities in linting can better help designers achieve significantly shorter turnaround time as well as where we see smart linting headed in the years ahead.