Minimizing Late-stage Functional ECOs: A Discussion with Todd Buzan

Q: Welcome, Todd. Let’s begin with a quick overview of the functional ECO solutions that Formality ECO provides.

Todd Buzan:

Well, several years ago we identified that even if an ECO is small and can be implemented manually, it is still an error-prone process. So we added some functionality to Formality to enhance the implementation of small, manual ECOs. We used to sell this interactive ECO functionality as ‘Formality Ultra’, however, we are now including this functionality as part of the base Formality package.

For the past 12 months we have been rolling out new, automatic ECO capabilities that we are calling ‘Formality ECO’. This is an entirely automated solution intended for large or complex functional ECOs that are difficult-to-impossible to implement manually.

Q: Can you elaborate on the interactive ECO functionality and how it is being used?

Todd Buzan:

To assist with implementing manual ECOs, we added functionality to Formality to first identify equivalent nets between the ECO’d RTL and the original netlist. We enable users to visualize the impacted logic cones and then edit the logic cones either graphically through Verdi nECO or by using a set of TCL commands to add or remove cells, nets, etc. The benefit is that users can edit individual logic cones and then verify just the logic cone they are working on. So, now it’s possible to do a very quick ‘what-if?’ analysis.

Q: What is the significance of Formality ECO and its automatic ECO functionality?

Todd Buzan:

For smaller manual ECOs, interactive functionality is enough. However, when the functional ECO starts to impact a larger part of the design or is complex in nature, for example, changes to state machines, then an automatic solution can provide significant value. Formality ECO was developed with the intention of enabling users to quickly generate a functionally-correct, timing-aware patch that minimizes the disturbance to the implemented design.

Q: What do you mean by “functionally-correct, timing-aware patch”?

Todd Buzan:

Well, for obvious reasons, the patch generated has to be functionally correct, however, other commercial solutions on the market are known to occasionally generate patches that are functionally incorrect. This can happen if, during synthesis, optimization results are different to when the original RTL was synthesized. In our case, Formality ECO understands the optimizations that Design Compiler and Fusion Compiler employ, so it’s functionally correct 100% of the time. Another limitation of other commercial solutions is that even if the patch is functionally correct, the patch often breaks timing. Since we enable users to use their original synthesis scripts and constraints when synthesizing the ECO’d RTL, the patch generated will be timing-aware.

Q: Is the scan chain impacted when registers are added or removed from the design?

Todd Buzan:

Sometimes, when you synthesize the ECO’d RTL the scan chain order is changed. Formality ECO will detect this and correct the scan chain order so that the original order is retained. Formality ECO does not add or remove registers from the scan chain, since this has a detrimental effect on the DFT flow, however, it does generate a report that tells the user which registers need to be added or removed.

Q: Typically, designers have a few netlist stages after the original synthesized netlist. How does Formality ECO handle this situation?

Todd Buzan:

After the ECO’d RTL has been synthesized and the patch to the original first netlist has been created, Formality ECO has a netlist flow that can rapidly go through all the subsequent netlists and patch those. It’s a very quick process and, of course, does not involve any more synthesis.

Q: Thank you for sharing this in-depth look into Formality’s ECO solutions!

Todd Buzan:

You’re welcome. Formality ECO is an exciting addition to the Formality family and we are looking forward to helping designers minimize the impact of late-stage ECOs on their design and schedule.