Multi-Die Chip Design: Multi-Chip Module Packaging Types

The electronic design industry is at an inflection point, where the intersection of scale and systemic complexity is giving us an opportunity to rethink semiconductor chip architectures to meet changing demands. On the one hand, chips are becoming more complex, driven by the needs of compute-intensive applications such as high-performance computing (HPC) and artificial intelligence (AI). At the same time, as Moore’s law wanes, designers are striving to continue advancements for optimal power, performance, area (PPA), and latency.

New innovations in IC design are emerging to address the challenges of the SysMoore Era—and advanced chip packaging technologies are certainly playing a major role. Multi-die chip designs, consisting of small dies, often on different process nodes and integrated into a single package, are proving to be a worthy option to meet aggressive PPA targets. A multi-die system-in-package (SiP) provides a number of benefits:

• Creation of products with more functionality
• Rapid creation of multiple SKUs by changing out the dies
• Reduced design risk when using proven dies
• Lower system power with increased throughput versus using two separate chips
• Optimized system form factor and lower system cost
• Increased system performance through low-latency dies compared to using two separate chips

The packaging landscape is dotted with an array of choices to support multi-die designs, from standard 2D packages to 2.5D advanced packages and 3D stacked die. There really isn’t a single package that works well for all products. The choice will be based on the design’s PPA as well as cost goals. In this blog post, I’ll share an overview of some of the newest multi-chip module (MCM) packaging types and highlight how die-to-die IP can support your design process with these packages.

Organic Substrate

At the lower end of the IO density spectrum, and with fewer die-to-die connections, is the organic substrate. This 2D type of standard packaging is relatively inexpensive and well established in the semiconductor industry. Because it lacks the fragile microbumps of its 2.5D and 3D counterparts and due to the maturity of the processes, organic substrate packaging tends to have higher yields. There are testability functions (with low-cost wafer-level screening for known good die), but there’s no requirement for test and repair of faulty connections.

Organic substrates are also marked by good heat dissipation, low warpage, and large SiP integration without reticle limitations.

Redistribution Layer (RDL) Fan-Out

Not yet in widespread use, the relatively new RDL fan-out packages provide a density that is similar to that of the silicon interposer but at less complexity and lower cost. Fan-out is an advanced packaging type that assembles one or more dies, leading to better performance and more IOs for a variety of IoT, networking, and computing applications. RDLs, consisting of copper metal connection traces, connect one part of a package to another electrically. In an RDL fan-out package, the RDL traces can be routed inward and outward; this allows for thinner packages with more IOs.

Silicon Interposer

In a silicon interposer, a connectivity die called an interposer is implemented in silicon to connect two dies. This 2.5D type of packaging allows for dense connectivity using microbumps, a vertical interconnect technology for stacked dies. Because of the complex assembly of this packaging type, as well as the delicate nature of microbumps, there are more associated yield issues. Packaging vendors address this through quality assurance measures as well as test and repair mechanisms in the die-to-die interface. Silicon interposers boast thousands of lines in parallel, and these lines are designed with logic to test connectivity, determine whether there’s a break, and reroute when needed. For example, if an interface has 1,000 lines, you’d design a PHY for 1,100 lines, providing 10% redundancy to allow for rerouting in the case of failures. However, with silicon interposers, it is difficult to screen wafers for known good die. In addition, this package type has reduced thermal dissipation and its interposer size is limited to the mask reticle size.

Hybrid Bonding

A type of 3D stacked packaging, hybrid bonding delivers the highest density along with power efficiency. There are through-silicon vias (TSVs) for connectivity. With two wafers bonded together and working as one, there’s no wasted power when driving the channels and power of each IO can be reduced as needed. Compared to interposers, hybrid bonding does present greater complexity and cost. It’s ideal for applications like AI training engines, which need substantial processing capabilities along with low latency. Stacking memory over the processor in a hybrid bonding package provides the performance and latency needed.

Die-to-Die Connectivity: The Enabler

While advanced packaging options allow engineers to scale and grow their designs in response to the demands of the SysMoore Era, die-to-die connectivity is an enabler. In the past, designers would first create their SoC and worry about the package somewhat later. Today, a co-design approach is necessary to bring together the system, the dies, and the package—and ensure they will all work together as intended. The glue holding together all of these parts? Die-to-die interfaces.

A die-to-die interface is a small block enabling communications between two or more dies sitting on a package. The interface needs to be optimized for the unique characteristics of each specific package type. For example, an interposer isn’t made to support very high speeds between channels, so high-speed die-to-die interface IP can fill the void here. Similarly, channel characteristics are better in an organic substrate, supporting longer reaches and higher data rates, so the interface IP can be selected accordingly.

The die-to-die interface industry is relatively young, with many interfaces developed in a proprietary manner, locking you into a design. Working with standards-based IP can provide the assurance of being able to evolve your design without worrying about interoperability issues or other design risks.

Four different alliances manage five standards across the packaging ecosystem:

• OIF oversees the XSR standard with data rates of 112G/224G for 2D packages targeting optical networking.
• CHIPS ALLIANCE oversees the AIB standard, which covers 6G data rates for bridge packaging, typically targeted for the mil-aero ecosystem.
• Universal Chiplet Interconnect Express oversees UCIe, with data rates of 16G/32G for 2D, 2.5D, and bridge package types. UCIe is targeted for scale and split use cases with streaming and aggregation with PCIe and CXL.
• The Open Compute Project is responsible for the BOW and OHBI standards, both defined for data rates of 8G/16G for 2D and 2.5D packages. BOW is targeted for cost-sensitive aggregation use cases, while OHBI is targeted for high-density scale and split cases for data centers.

Over time, some of these standards may become less relevant based on market needs. Out of all of these, UCIe has the potential to be a truly universal and comprehensive standard for die-to-die interfaces. While delivering the most compelling PPA metrics, it also covers the widest range of use cases as well as all package types for multi-die designs. It is a complete protocol stack enabling raw user-defined streaming, PCIe (non-coherent), and CXL (coherent). With support for data rates of up to 32Gbps per pin, UCIe also is future proof. The emerging specification has the support of a broad ecosystem spanning all industry segments: hyperscalers, CPU vendors, foundries, outsourced semiconductor assembly and test (OSAT), IP vendors, and aggregators.