Synopsys Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial →
Table of Contents
Whether your technology enables explorations at the edges of the universe, connects people on earthly roads less traveled, or something in between, what you don’t want is for your silicon to fail. Today’s mission-critical SoC applications require very-low defective parts per million (DPPM). As complexity of semiconductors increases, structural testing of devices becomes more challenging. The number of patterns to test the device has increased significantly, coupled with the fact that there are a limited number of general-purpose IO (GPIO) pins to perform the tests. These IO pins also lack the bandwidth necessary to test today’s designs efficiently.
Limited pins and bandwidth can cause a bottleneck that can increase your test time and test costs. You are also limited to running patterns only in manufacturing—if something goes wrong in the field, you are out of luck.
Semiconductor innovation has leapt ahead in recent years. As the benefits of Moore’s law wane, there are new technologies that are taking us to the SysMoore era of systemic complexity, helping us realize next-gen performance-power-area (PPA) gains. Semiconductors are evolving to meet the demands coming from high-performance computing, hyperscale data centers, AI and ML, automotive, mobile, 5G, IoT, defense, and more. It’s time for testing methodology to evolve, too. High-speed functional serial interfaces are a great path forward for resolving structural testing challenges in advanced designs. Read on to discover more about how AWS is leveraging them in their silicon testing strategy.
When JTAG and GPIO Pins Are Not Enough
GPIO or Joint Test Action Group (JTAG) pins have been the main method to access scan chains and test access ports (TAPs) for structural testing. This means structural testing can only be done during the automatic test equipment (ATE) phase, or production, and the scan bandwidths are limited by GPIO pin speed. To connect device-internal scan chains to ATE, you must dedicate some pins. Those pins are sacrificed for testing and cannot then be used in your final design. To get around some of the bandwidth limitations, you can use lossy compression methods for the scan outputs, which reduces the number of output pins required at the expense of reduced scan diagnostic resolution.
You can also use a process of serial streaming which uses address code or time multiplex techniques to reduce the pins required for scan test. But, even with these solutions, GPIO pins are quickly approaching the ceiling of what they can do for the structural testing process and cannot be leveraged during all phases of the silicon lifecycle.
Why You Should Test Your SoC Using Functional High-Speed Interfaces
Moving to existing high-speed functional interfaces for your production testing, such as PCI Express® (PCIe®) or Universal Serial Bus (USB), or another interface, is a novel approach that can solve a lot of issues:
- You don’t need additional pins
- The bandwidth is high
- You can access structural testing during the entire silicon lifecycle
In fact, getting scan input on devices in the field can change the game for silicon lifecycle management. It doesn’t matter where your device is deployed, whether it’s in a satellite, or a car, or somewhere in the router. By using these interfaces for testing, you can check the status of your device while it’s in the market. And with that information, you now have a choice in how you address those issues to manage the life of your product.
How to Use Serial Interfaces for High-Bandwidth Silicon Testing
Enter the Synopsys SLM High-Speed Access and Test (HSAT) IP plus the Synopsys Test Adaptive Learning Engine (ALE) software, together providing the solution for high-bandwidth silicon tests. Our solution leverages high-speed functional interfaces instead of using GPIO and JTAG pins, resolving the bandwidth issues. It also allows structural testing to be done during your system-level test (SLT) and in-system test (IST) phases. You can do this because these interfaces allow you to access your design for test (DFT) or silicon monitoring network over the existing functional serial interfaces. It also allows you to reuse the same high-speed test packets and repeat the manufacturing testing in the ATE, SLT, or IST stage.
The Synopsys SLM solution is flexible because it supports a variety of interfaces: PCIe, USB, mobile industry processor interface (MIPI), serial peripheral interface (SPI), 1149.10, and more. Plus, the soft IP is configurable, handling data translation and forward translation, translating the automatic test pattern generation (ATPG) into the patterns needed by the scan chains or some of the built-in self-test (BIST) engines. And on the way out, it does the reverse mapping, to give you virtual pin location and cycle logs.
General Architecture: HSIO Scan
Because the Synopsys ALE software can be added to SoC testers like Advantest’s V93000, it means there is an ecosystem and a comprehensive, seamless solution. The Advantest V93000 ATE comes with Advantest SmarTest software, which can be extended with Synopsys ALE embedded. Recently released Advantest Link Scale cards provide the hardware capability needed to support PCIe and USB ports. And no matter what stage of the silicon lifecycle you are in—wafer or die test, final test, SLT, board-level test (BLT), or IST—you have a common debug platform.
AWS Decreases Silicon Testing Times and Monitors the Entire Silicon Lifecycle
Amazon Web Services (AWS) had been facing some DFT challenges with their advanced high-speed ML semiconductors, Inferentia and Trainium, when the GPIO had decreased from 318 to 64 pins between generations. It impacted the testing, resulting in sub modes and test cycle times that were nine times longer. Using the Synopsys SLM solution and Advantest V93000, they were able to reduce their test cycle times back to the level of previous generations despite the drastically reduced pin count. In addition, they gained visibility of functional performance—the ability to track and monitor the health of their chips during ATE, PSV, SLT, and IST phases so that their customers wouldn’t be as impacted by aging and degradation.
This was done initially on limited bandwidth, instead of the full bandwidth, and the results were so successful that AWS plans to use more of the bandwidth in the near future to reduce the test times even further.
Check Out Our Demo on High-Speed Interface Ports for Silicon Testing
By leveraging your existing functional high-speed interface ports for testing, you’ll reduce test time and cost and be able to monitor the health of your product long past production, especially important for safety-critical applications. And with an ecosystem that’s growing, you can be assured that your test path forward is a smooth one.
If you are interested in learning more, contact us for additional information and a demonstration.