SRAM Margin Analysis Workflow

Helping designers in their quest for better SRAM design power, performance, and area while maintaining high reliability.

Transcript:

The design and verification of memory chips grow more challenging with each new generation of technology and each new demanding application. Big data applications across AI, automotive, and 5G compel memory vendors to constantly deliver higher performance, higher power efficiency, and higher capacity in the chips they develop.

Memory design verification tools must keep pace with these changing requirements and deliver higher capacity, faster runtimes, and advanced reliability analysis with a unified workflow to support designers in their quest for better power, performance, and area, while maintaining high design reliability.

PrimeSim Continuum is a unified workflow for circuit simulation technologies built on next-generation SPICE and FastSPICE architectures. The continuum includes PrimeWave Design Environment and PrimeSim XA, PrimeSim SPICE, PrimeSim Pro, and PrimeSim HSPICE.

PrimeSim HSPICE is the gold standard for SPICE accurate simulation and continues to serve as the signoff reference for foundation IP and signal and power integrity. PrimeSim XA is the solution of choice for SRAM designs, featuring breakthrough topology recognition, partitioning, and dynamic synchronization technologies, to deliver superior fast SPICE performance while meeting stringent accuracy requirements for SRAM timing, power, and margin analysis.

SRAMs are the critical building blocks of today's semiconductor chips. They are most commonly used as on-die cache for hyperconverged SoCs, serving mobile and high-performance compute applications, as well as low-power microcontrollers for IoT. The heart of an SRAM is the memory array made up of millions of bit cells, the basic building blocks that store data in the form of a 0 or a 1. The data is written into and read from the array through the SRAM periphery made up of sense amplifiers and I/O drivers. The address control logic helps select where to write into or read from.

The primary care for SRAM designers is ensuring that data is written and read back correctly. SRAM designers typically rely on corner simulations and high sigma Monte Carlo analysis to verify read/write operations in the presence of non-idealities, such as device variation, device leakage, and extreme process, voltage, and temperature corners. But such traditional brute force methods are not adequate to identify and mitigate design weaknesses, resulting in suboptimal design power, performance, and area choices, low design yields, and higher field returns.

Synopsys offers a high sigma margin analysis flow that allows SRAM designers to assess the weakness of their designs. The workflow supports both a GUI-driven use model, using PrimeWave Design Environment, and a batch mode use model. The design workflow leverages best-in-class engines, PrimeSim HSPICE, PrimeSim Advanced Variation Analysis, and PrimeSim XA, to enable accurate read and write margin analysis with extended coverage.

Users can launch the workflow from within PrimeWave Design Environment. In the first step, PrimeSim HSPICE is used to characterize SRAM bit cell noise margins. The designer uses that information to optimize read/write circuitry. Next, PrimeSim Advanced Variation Analysis is used to generate high sigma models for critical SRAM building blocks, such as bit cells, sense amplifiers, read/write assist circuitry, self-timed clocks, and I/O multiplexers, and buffers.

Traditional Monte Carlo methods require billions of samples for high sigma analysis. PrimeSim Advanced Variation Analysis uses advanced machine learning algorithms to accurately predict non-normal circuit behavior across four to six sigma, with 100 to 1,000 times faster throughput. The worst case sigma corner for each building block is selected and imported seamlessly into a full instance netlist. This full instance netlist is then simulated using PrimeSim XA, thus enabling a high sigma characterization. Repeating these steps across multiple PVT corners enables SRAM designers to create the shmoo plots as shown.

The SRAM margin analysis workflow-- based on PrimeSim HSPICE, PrimeSim Advanced Variation Analysis, and PrimeSim XA-- uses 100 to 1,000 times fewer simulations compared to traditional Monte Carlo analysis to accurately assess high sigma margins of an SRAM design, helping designers shift left in the overall design process. It also allows designers to analyze and optimize design margins on very large SRAM designs, something that was previously not possible.

PrimeSim Continuum solutions-- helping designers in their quest for better SRAM design, power, performance, and area, while maintaining high reliability.