StarRC Standalone Netlist Reducer: Achieving Practical Simulation Times

Insights on StarRC Standalone Netlist Reducer

With the ever-growing size of extracted netlists, parasitic optimization is key to achieve practical simulation run times. Key trade-off for any netlist reducer is accuracy vs netlist size. StarRC Standalone Netlist reducer provides the flexibility to optimize your netlist on a per net basis. User has total control of trading accuracy of some nets versus netlist optimization. Yet another feature from StarRC to provide flexibility to the designer.

Transcript:

Hi there, my name is Senthil Annamalai, and I am a Senior Staff Product Engineer at Synopsys supporting the extraction tools. In this video, I'm going to cover the features and benefits of StarRC Standalone Netlist Reducer.

With the ever-growing size of extracted netlists, parasitic optimization is the key to achieving practical simulation runtimes. The key trade-off for any netlist reducer is accuracy versus netlist size. At Synopsys, we have a category of netlist reducers, each addressing a specific need based on the design application.

As seen in the image, StarRC has a built-in reducer that generates a globally optimized netlist SPF or SPEF. Recently, we introduced the StarRC Standalone Netlist Reducer, which provides flexibility to optimize your netlist on a per-net basis. Users have total control over trading accuracy of some nets versus netlist optimization. Our FastSpice simulators have an inbuilt netlist reducer to make the necessary trade-offs between accuracy and simulation runtime.

The main use case for Standalone Netlist Reducer is high-accuracy analog circuits, where you want to improve the simulation runtime without sacrificing accuracy on critical nets. StarRC Standalone Netlist Reducer can handle SPF and SPEF inputs, supports gzipped files, and temperature sensitivity. It optimizes the number of nodes as well as the number of parasitic Rs & Cs.

In the image, you see a typical design flow for a standalone reducer. We have highlighted two design cases: a DRAM and a VCO. For the DRAM case, the comparison is between StarRC inbuilt reduction with simulation reduction versus inbuilt plus standalone reduction with simulation reduction. Here, we see greater than 30% reduction in file size and over 1.3x improvement in simulation runtime.

For the VCO design, the comparison is between StarRC Standalone Reducer and a third-party reduction tool. Here, the reduction achieved is similar or better than the third-party reducer tool, and the simulation runtime improves by 1.3x with the third-party simulation tool.

StarRC is the golden signoff extraction tool and is always adding new features to improve productivity, usability, and flexibility for our valued customers. StarRC Standalone Netlist Reducer provides a seamless experience with StarRC and improves TAT (Turn-Around Time) for the end user.

Thank you for watching this video.