Hardware-Assisted Verification: Unlocking the Future of Chip and System Design

Driven by the ever-growing demand for computing power, autonomous systems, and next-generation architectures, the semiconductor industry is experiencing a never-before-seen shift toward pervasive intelligence. As a result, silicon complexity and the software content in systems and products continue to increase at an exponential rate. 

Look at the automotive industry, for instance. Manufacturers and their suppliers are re-architecting vehicles and system-level components with new and hotly debated electrical/electronic (EE) architectures that help create differentiation. This trend extends to other markets such as industrial automation, high-performance computing (HPC) data centers, and aerospace, with software-defined systems driving massive computing power, both at the edge — in the latest smartphones, cars, and cameras — and within core data centers where the data converges. 

With AI now influencing almost every aspect of modern technology, chip designers are presented with new challenges to ensure their products meet performance expectations and operate reliably and efficiently under relentless computational demands. These changes are pushing the limits of traditional design and verification methodologies, creating a need for innovative solutions to address modern chip and system architectures.

Enter: Hardware-assisted verification (HAV), an essential approach that helps engineers improve design behavior to manage complexity and ensure systems function seamlessly in real-world applications.

In this blog post we’ll explore the role of HAV, examining different use cases, AI’s role in shaping new design requirements, and the need for flexible industry solutions to develop sophisticated chips.

Developers have two primary options. They can either build these blocks in-house, leveraging their own expertise and proprietary designs, or they can license them from industry leaders such as Synopsys. But the journey doesn't end with IP selection, integration, and chip creation. Silicon chips are subsequently integrated into boards, forming the backbone of powerful accelerator systems. These systems are then designed to drive and execute a vast array of software, from low-level drivers to high-level AI frameworks and applications. This holistic strategy ensures that each element works harmoniously, maximizing efficiency and performance across the entire AI acceleration ecosystem.

While this progression from IP blocks to fully-fledged AI accelerator systems may seem straightforward, the reality is far more nuanced. The key question is: What needs to be done to ensure these systems function as intended at every stage of the process and from different perspectives like functional correctness, performance, and power?

Functional verification through RTL regressions, IP performance validation, and compliance checks are essential to confirm that the IP behaves as expected in a system-level environment. Early-stage performance analysis, low power assessments, and test generation are equally crucial to ensuring efficiency and reliability. Additionally, key considerations such as safety, security, and silicon lifecycle management must be incorporated to meet modern design demands.

As products evolve and the complexity of workloads and systems increase, traditional verification techniques become less viable and new methodologies must be utilized. 

Integrated verification engines — from simulation-based tools at various abstraction levels to hardware-assisted solutions like emulation and FPGA-based prototyping — enable efficient execution of extensive workloads, addressing crucial scalability needs. Cloud-based solutions are particularly valuable in this context to further optimize performance and cost-efficiency, allowing simultaneous processing of numerous workloads and regressions through a hybrid approach utilizing both on-premises and cloud-based resources.

The key to effective verification lies in seamlessly transitioning between different use cases, from rapid early-stage RTL debugging to high-performance software workload validation. HAV platforms that are configurable and efficiently address this spectrum are essential to validate real-world chip and system design complexities that require real-world workloads. With the insatiable demand for verification cycles, design teams must also be conscious to achieve the best ROI for each of the verification engines. While there is no engine that fits all use cases, we have entered an age in which re-configurability of HAV setups across projects or even within projects becomes a critical component of ROI considerations, joining the classic concerns of direct acquisition costs and indirect costs like power consumption of verification setups. 

Ultimately, an adaptable verification architecture is crucial, accommodating diverse user requirements and use cases while remaining agile enough to meet future technological demands in this ever-evolving landscape.