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Synopsys Webinar | Available On-Demand
Leveraging functional patterns is crucial for achieving high defect coverage and reducing defective parts per million (DPPM) levels. Synopsys VC Z01X fault simulator offers enhanced fault coverage in manufacturing test flows, complementing ATPG tools like Synopsys TestMAX ATPG. In this presentation we will delve into unique coverage scenarios, such as resets and clocks blocked during ATPG mode. We'll also highlight the benefits of VC Z01X robust support of the SystemVerilog language. Finally, a practical flow discussion will equip viewers with best practices to get started.
Speakers
Robert Ruiz
Product Management, Sr Director
Synopsys
Robert Ruiz is a product management director responsible for strategy and business growth of several verification products at Synopsys. Robert has held various marketing and technical positions for leading functional verification and test automation products at various companies including Synopsys, Novas Software, and Viewlogic Systems. He has more than 30 years of experience in advanced EDA technologies and methodologies and spent several years designing application-specific integrated circuits (ASICs). Robert has a BSEE degree from Stanford University.
Kirankumar Karanam
Applications Engineer, Manager
Synopsys
Kirankumar Karanam is Staff Application Engineer at Synopsys. He currently oversees various customer deployments of Synopsys FuSa verification solutions worldwide. He also works with Synopsys functional verification offerings such as VCS, Verdi, and more. He holds M.S in Software Systems from BITS, Pilani.