Don’t Take the Risk, Formally Verify Your RISC-V Cores

According to a recent Semico Research report, the RISC-V Core IP market is expected to grow at a 34.9% CAGR through year 2027. With increasing popularity, it is of utmost importance that the RISC-V Core IPs are secure and bug free. ​

In this joint Synopsys webinar with SyoSil, will discuss how to use formal verification to ensure functional correctness and security of RISC-V Cores. We will cover the high-level formal verification goals and example tasks so attendees can obtain a comprehensive view of the many facets of RISC-V Core verification using formal technologies. We will explore a specific case study that uses the so-called ‘S2QED’ methodology to verify a scalar five-stage RISC-V Core. We will also show a demo for this case study using Synopsys VC Formal. ​

The attendees will walk away with a comprehensive understanding of the formal verification requirements for RISC-V Cores to ensure functionality and security, as well as specific examples of using formal property verification to find intra- and inter-instruction design bugs. ​