Meeting Complex Design Requirements for Integrated ADAS Domain Controller SoCs

Advanced driver assistance system (ADAS) applications are the fastest growing segment of the automotive electronics market with an expected growth rate of more than 10% per year, reaching $62.7 billion by 2024 (Variant Market Research, Global ADAS Market Report). System architectures are evolving rapidly, taking advantage of advanced FinFET technologies to integrate complex functions for lowest cost and power. Traditionally, the electronic control units (ECUs) for individual ADAS applications have been placed throughout the car, with the forward collision avoidance ECU located in the windshield, park assist ultrasonic sensors throughout and the processor in the rear. ECUs integrate multiple ADAS applications into centralized domains to combine ADAS functions. The new class of integrated domain controller ECUs utilize data transferred from the car’s remote sensors such as cameras, LiDARs, radar, and ultrasonics to the integrated domain controller for processing by a high-performance ADAS system-on-chip (SoC) (Figure 1). Centralized, integrated ADAS domain controllers require higher computing performance in a smaller footprint, while consuming less power, compared to distributed systems.

Integrated ADAS domain controllers are subject to SoC-level automotive certification which remains a mandatory requirement for designers. The IP in the integrated ADAS domain controller SoC must also meet the highest Automotive Safety Integrity Levels (ASILs), must be designed and tested for grade 1 and/or grade 2 temperatures, and must fully adhere to the automotive quality management process. In addition, to meet power and performance requirements, designers are moving to advanced FinFET process technologies.

This article describes how automotive-certified logic libraries and embedded memory compilers can provide a solid foundation for, and accelerate the development of, integrated automotive ADAS domain controller SoCs. 

Integrated ADAS Domain Controller SoC Architectures

Figure 2 shows a typical architecture of an integrated domain ADAS controller that consolidates multiple controllers, sensors, and subsystems.

This central ECU must process multiple data streams of real-time, high-speed video, radar, and ultrasound and LiDAR subject to high temperature environments while making key decisions that can affect the safety of human lives. These requirements place a set of tough challenges on the SoC design, the SoC designers, and the Foundation IP used to build these SoCs.

Challenges for Foundation IP for Centralized Domain Controllers

The main challenges for Foundation IP for centralized domain controllers include ease of integration, low power, and high reliability, quality, and safety.

Ease of Integration

Centralized ADAS controllers contain multiple 64-bit processors with additional image processors to manage cameras, neural network processors for deep learning, graphics processors for rendering displays, and embedded vision processors for inference engines. These processors often need application accelerators for higher performance and power minimization. Integrating these functions on a single die is driving SoC designers to advanced FinFET nodes such as 14/16nm and 7nm. Moreover, centralized controllers incorporate the functionality of previous distributed designs that may contain legacy circuits or legacy voltages/temperatures that require solutions that include customized PVT corners, logic cells, and/or memory compilers.

Power

Each of these integrated controllers must fit the power envelope for the device for where it is placed in the automobile. This power restriction is not because of battery life issues as with mobile phones. Integrated combustion engine (ICE) automobiles each have at least a 50 Amp hour 12V battery and electric vehicles (EVs) have 20 Kilowatt hours of battery. The challenge is that integrated ADAS controllers SoCs generate heat that must be dissipated. For example, the widely publicized second generation ADAS controller Nvidia Drive PX at 120 Watts is water cooled, which places severe restrictions on where the device can be placed in the automobile and is a major contributor to the cost and reliability of the system.

Total system costs rise dramatically when moving from plastic packages to ceramic, and then with cooling strategies from free air to multiple types of heatsinks to fans (which make noise) to simple forced water (needs plumbing) and finally to microchannel cooling (expensive high-pressure pumps that take advantage of phase change energy by allowing the coolant to boil). To avoid the use of these costly cooling systems, power must be minimized at each stage of design starting with the low power circuits in the Foundation IP, and including the processor/accelerator design and the software algorithms that perform critical functions. 

Reliability

Reliability is defined by defective parts per million (DPPM) under a set of temperature conditions over time as specified in the mission profile. Whether it is an IC, a system, or individual IP components, DPPM must meet reliability specifications under a wide range of temperatures. For ADAS applications, Grade 2, Grade 1, and Grade 0 temperature ratings are commonly used. Grade 0, the most stringent, is reserved for under the hood and drivetrain applications where a junction temperature can go as high as 175C. Grade 2 is the base level for automotive applications, with reliability requirements similar to those found in consumer electronics. Functionality should be validated up to 125°C junction temperatures. Grade 1 ratings require that functionality is be validated up to 150°C junction temperatures, with reliability of <1 DPPM. Electromigration (EM) profiles can be application specific for ADAS implementations and memories must integrate error-correction checking (ECC).

Foundation IP for ADAS controllers must include EDA views for timing and power so that SoC designers can validate the reliable performance of their SoC over the life of the product per the mission profile. Aging corners simulate the state of the silicon at the end of its useful life as specified in the mission profile. They enable designers to measure how the silicon slows down over time (while leakage improves) and to assure functionality at end of life. EM corners enable power analysis to verify that circuits will not fail EM limits given the operational activity of the circuits with the loads placed on each output. Physical EDA implementation tools can provide solutions to those violations before tapeout by decreasing fanout or using higher drive cells. Finally, burn-in corners can be used to simulate the behavior of the device when going through accelerated life testing. This testing uses extreme oven temperatures with overdriven voltages design to prove out end of life models during high temperature operating life (HTOL) tests.

Quality

The TS 16949 quality management standard was first developed in 1999 and has since become one of the most widely used standards in the automotive industry and is considered a robust management framework. Synopsys has invested a great deal of time and resources to enhance its IP development processes to fully support TS 16949 documentation requirements. Should SoC designers need to do an audit of quality management systems, Synopsys is able to provide the necessary documentation for all automotive IP.

Safety

Safety is governed by ISO 26262 that requires companies to not only apply functional safety to their design and manufacturing processes, but that they demonstrate that they have a functional safety culture engrained within the organization, with all the required processes and competencies in place. Manufacturers must ensure that they can demonstrate expertise in how ISO 26262 relates to their IC designs, either by training existing staff, hiring functional safety specialists, or outsourcing the work to third-parties. DesignWare Memory Compilers are certified as ASIL D Ready to meet the highest integrity requirements.

Logic Libraries for ADAS Domain Controllers

Area-efficient and power-efficient logic is required for massively parallel, matrix multiplication circuits that often form the heart of embedded vision accelerators, neural network processors, and image processors. The core of these types of circuits are multiply accumulators (MACs) that include adders, compressors, complex AO/OA gates, and registers. These computation engines can include both integer and floating-point operations. Critical circuits include 8-bit integer with 16-bit floating point MACs and support conversions between integer and floating-point formats in today’s accelerators, especially neural processors used for deep learning.

Optimal Numerical Precision

Reducing numerical precision of scalar data is a key technique in minimizing energy in deep learning because most deep learning algorithms applying weights to scalar data are quite tolerant of small round-off errors. For example, an 8-bit fixed-point adder consumes 3.3X less energy and 3.8X less area than a 32-bit fixed point adder and 30X less energy and 116X less area than a 32-bit float adder. Reducing the precision also reduces the memory area and energy needed to store this typically sparse matrix data and reduces the memory bandwidth issues that can quickly become the system performance bottleneck or dynamic power hotspot. Integer and floating-point MACs use a variety of multiplier types such as Booth, Wallace tree and a wide variety of adders-carry-look-ahead, carry-save, and carry-select.

Power Minimizing Logic Libraries

DesignWare Logic Libraries contain a rich variety of fast and efficient half and full adders, XORs, compressors, Booth encoders, multiplexers and flop and latch families, including multi-bit, for partial products and other storage. To minimize the power consumed in the clock tree, asynchronous logic may provide the next breakthrough in power optimization of deep learning accelerators. The power efficiency of MACs, which are repeated millions of times on embedded vision processors, is measured by a figure of merit of computation throughput per unit of energy, such as at GMAC/s/W or Giga multiply per second per Watt. The choice of optimal numerical precision and energy-efficient arithmetic logic cells can be critical in minimizing power. Figure 3 shows the Logic Elements used in an embedded vision processor that contains arrays of both integer and floating point MACs.

Memory Compilers for ADAS Domain Controllers

Optimized for low power, high performance, and high density, DesignWare Memory Compilers offer advanced power management features such as light sleep, deep sleep, shut down, dual power rails, and write assist, allowing designers to meet the stringent low-power requirements of today's ADAS domain controllers. DesignWare Memory Compilers are closely coupled with the DesignWare STAR Memory System™, providing an integrated embedded memory test solution to detect and repair manufacturing faults for the highest possible yield with least impact on chip area. DesignWare Memory Compilers are silicon-proven with billions of chips shipping in volume, enabling designers to reduce risk and speed time-to-market. DesignWare Memory Compilers for automotive applications and DesignWare STAR Memory System have received full ASIL D safety certification after undergoing extensive safety audits and reliability margin analysis.