Addressing Functional Safety in SoCs with Test Solutions

Introduction

Over the last few years, it has become clear that automotive will become a key growth market for semiconductors over the next decade. Multiple factors are driving increased semiconductor and memory content in automobiles such as regulation, sustainability, safety and security, e-mobility, and convenience.

With automotive OEM vendors demanding reduced risk and high product quality, automotive IC designers must address functional safety concerns by demonstrating ISO 26262 compliance while achieving stringent safety levels such as ASIL D. These designs should meet or exceed AEC-Q100 and/or JEDEC guidelines in terms of IC qualification. Designers of safety-critical automotive ICs must demonstrate a high degree of confidence to their customers in the designs’ tools and IP they use. Further, the foundries where these automotive ICs are manufactured need to demonstrate high product quality as laid out by standards such as TS16949.

Challenges in Designing Automotive SoCs

Test challenges for ADAS IC designers can be categorized into the various phases of an automotive IC lifecycle:

During design:

• How can I achieve high test coverage (despite newer FinFET memory fault types) to achieve low DPPB?
• How can I minimize design-for-test (DFT) overhead on a SoC’s power, performance, and area to remain competitive?
• How can I integrate and test a variety of analog, digital, and mixed signal IP blocks procured internally as well as from third party external vendors?

During early silicon bring up and production:

• How can I efficiently debug and diagnose silicon to localize types of memory faults and failing (X,Y) coordinates?
• How can I accurately measure critical clock frequencies and conduct process monitoring?
• How can I test early silicon in the lab rather than waiting for ATE bench diagnostics which may be located elsewhere?

Out in the field:

• How can I achieve efficient POST and repair?
• How can I deal with increasing multi cell upsets at advanced geometries and keep FIT rates low?
• How can I manage periodic in-system test and mission mode testing to meet ISO 26262 requirements?

Synopsys Functional Safety Test Solution for Automotive ICs

As shown in Figure 1, Synopsys' functional safety test solution includes the ASIL D Ready Certified DesignWare® STAR Memory System®, STAR ECC Compiler, STAR Hierarchical System, and DFTMAX™ LogicBIST software qualification kit, as well as ARC® HS processors, providing test and repair of memory and logic blocks with automatic test integration and validation of analog/mixed-signal IP. This solution leverages an industry-standard IEEE1500/1687-based infrastructure while supporting both star and ring configurations that can be used to balance SoC test time, floor planning challenges, and other system constraints. 

Managing Memory BIST & Repair for FinFET-Specific Defects

DesignWare STAR Memory System offers memory BIST and repair capabilities using algorithms optimized for FinFET-specific transistor defects. STAR Memory System can create either a shared or dedicated wrapper for the on-chip memories which will encapsulate the comparator logic and reconfiguration information needed to perform row, column or row, and column-based memory repair. Any number of memory and wrapper combinations can be instantiated under a STAR Memory Processor which is responsible for scheduling and executing the programmable algorithms. To enable IP block re-use in hierarchical designs, the processor may then be connected to a STAR Memory System /STAR Hierarchical System sub-server. Each sub-server may then be connected to the top level server on individual rings. The function of the top level server is two-fold: to connect to the outside world via JTAG/TAP based interface and read/store repair information via an interface to OTP/foundry e-fuse (not shown in Figure 1). This architecture enables the user to efficiently test multiple rings of IP cores concurrently (to reduce overall test time) while allowing sequential test of some IP (to mitigate system level EM/IR concern as an example) on the same ring.

For conventional ATE vector generation and post silicon debug/diagnostics, Yield Accelerator (part of the STAR Memory System solution) generates the needed patterns in WIGL, STIL or other commonly used formats using the SMS generated design database. Yield Accelerator can generate firmware targeted for users planning to use the ARC HS processor as the functional safety manager. The Silicon Browser utility (part of the STAR Memory System solution) enables support for early silicon prototype debug on a low cost PC/laptop that uses a convenient USB-to-JTAG cable. 

Improve Reliability During In-System Operation

STAR error correction code (ECC) compiler circuitry detects and corrects single-bit and multi-bit upsets in embedded memories to improve reliability during in-system operation (see STAR ECC wrapper in Figure 1). STAR ECC is independent of memory vendor and offers encoding/decoding with user selectable algorithms such as Hamming or Hsiao to tradeoff area vs performance. Most importantly, STAR ECC helps designers meet ISO 26262 requirements such as:

• Fast reaction time for reporting detected errors during POST or mission mode (in-system operational mode)
• Hardware error injection (without corrupting real data) to determine behavior of a system during abnormal operation
• Checking the address (and data) bits of memory to detect any address decoder faults

Familiar Flow for LogicBIST

DFTMAX LogicBIST software qualification kit provides a synthesis-based solution for rapid in-system self-test of digital circuits. Because it is built into the Design Compiler, it optimizes timing, power, and area — and reduces routing congestion for both test and functional logic.

The Synopsys logic BIST flow is similar to other DFTMAX flows. Starting with an RTL or netlist, it synthesizes logic BIST and creates a testbench. There is an intermediate step which programs data from TetraMAX ATPG into the design after final pattern counts and coverage have been decided upon. The self-test itself is based on generating pseudo-random patterns on-chip, which are different than the patterns TetraMAX ATPG generates for manufacturing tests. Links between DFTMAX LogicBIST, DFTMAX Ultra compression, and TetraMAX ATPG accelerate tasks such as calculating the seed and signature, and analyzing and inserting test points. For the manufacturing test, the logic BIST registers are inserted into scan chains along with the functional logic. Either scan or compression modes can be set up when conducting a manufacturing test.

Hierarchical Test for Mixed Signal IP

DesignWare STAR Hierarchical System ensures high coverage using hierarchical test for mixed signal IP blocks (e.g., PVT sensors, PLLs, DDR/LPDDR, USB, MIPI PHYs) while enabling re-use of IP production/manufacturing patterns. STAR Hierarchical System can read the IP description using its native format or convert it from an IEEE1687 specified format ICL and PDL. The production-ready patterns for Synopsys DesignWare IP modelled in STAR Hierarchical System is very convenient for DFT engineers to leverage as the number of these manufacturing and characterization patterns can exceed a hundred with the increasing number of test modes (e.g, BERT, initialization, loopback) needed for PHY IP at 7-nm and smaller technologies. The ability to dynamically change IP test scheduling, even post silicon via the JTAG port, offers additional flexibility to production engineers concerned with optimizing test time. In addition to supporting DesignWare IP from Synopsys, the STAR Hierarchical System supports mixed-signal IP developed in-house or by third-parties.

A key capability of the STAR Hierarchical System is its Measurement Unit, which detects process variation and device aging (soft monitoring). As opposed to off-chip measurements, which are prone to jitter especially for high frequency signals, the Measurement Unit is embedded and proven up to 3.2GHz with a high degree of precision on almost every Synopsys Foundation IP test chip. It can be leveraged by IC designers as well as foundries to measure chip parameters on-silicon. The Synopsys-patented pulse delay measurement methodology deployed in the Measurement Unit offers PLL characterization functions and built-in self-test (BIST) for high-speed clocks without any additional fractional or high-speed PLLs other than the available low-frequency test clock. The different modes that the Measurement Unit supports are shown in Figure 2. 

Using the existing on-chip STAR Measurement System/ STAR Hierarchical System infrastructure, measurements can be captured via the Silicon Browser capability on a PC or a laptop using a convenient USB to JTAG cable. There is no limit to the number of Measurement Units that can be embedded in the SoC as the gate count is just a few hundred gates. 

On-Chip Safety Manager

The highly configurable DesignWare ARC Processors with Safety Enhancement Package (SEP) integrate hardware safety features such as ECC and parity support, user programmable watchdog timer, lockstep interface, lockstep monitoring system, and optional memory protection unit. The ARC HS processor selects and activates in-system tests by functioning as an on-chip safety manager. The interface between the ARC HS processor and STAR Memory System/STAR Hierarchical System has been tuned and validated to enable initiation and scheduling of the BIST activities across the many IP blocks in the SoC and can be fully controlled by system software.

Synopsys’ Functional Safety Solution

By providing a pre-verified functional safety test solution, Synopsys is helping designers ensure high test coverage, achieve low DPPB, and reach the required automotive safety integrity levels (ASILs) of their automotive designs. The solution:

• Offers full lifecycle control of automotive SoCs from design, early silicon bring-up, production test to field deployment by re-using IEEE1500 based on-chip infrastructure
• Unifies observability and/or test and repair for all key IP blocks on the SoC – embedded memories (SRAMs, register files, CAMs, multi-ports), digital logic blocks/cores as well as analog and mixed signal IP blocks to provide high defect coverage
• Includes an on-chip safety manager (ARC HS Processor) which manages flexible periodic and mission mode testing. The safety manager can:
  • Activate POST with the dedicated pin interface in STAR Memory System/STAR Hierarchical System Servers either during production test or in-system to initiate logic BIST, memory BIST, and any processor diagnostics
  • Control which rings of memories are tested in mission mode by bypassing those that are not needed. Further only the test algorithms (typically with reduced complexity) to be run during mission mode can be specifically selected based on the amount of time available
  • Automatically pass the control back to the system after a pre-specified memory testing interval (e.g., 100ms or 5000 clock cycles) OR when an interrupt is received during mission mode
  • Be configured to keep track of tested/untested memory segments to allow deferred contiguous testing
  • Communicate to the host system with alerts if the memories or cores are available for test or are not ready for mission mode operation

With full support for the widely used APB interface, the designer does not need a protocol conversion unit and can quickly leverage the provided high level example firmware and diagnostic software tests to develop system specific test scenarios.