Anatomy of an Integrated Ethernet PHY IP for High Performance Computing SoCs

Priyank Shukla, Staff Product Marketing Manager, Synopsys

For example, most personal computer users are familiar with “Ethernet cables” in their laptops/PCs. Figure 1 shows a simplified block diagram describing how data is transferred to and from the processor over an Ethernet cable. In this use case, Ethernet data frames (packets of data), assembled by Ethernet MAC in the CPU, travel across the mother board (a printed circuit board) through MII/GMII, defined by the IEEE802.3 standard, before reaching an Ethernet PHY which transmits electrical signals over twisted pair cables through RJ 45 connectors.

Figure 3 shows data packets traveling in a data center, originating from a processor in one of the rack units of a server farm. Data from the processor goes to the network interface card (NIC) through a PCIe interface. The network interface card creates Ethernet frames by implementing MAC functions. The frames travel to the Top-of-Rack (ToR) switch through a twin-axial copper PHY or DAC cable. Depending on the DAC cable length and the switch silicon in ToR rack unit physical location, retimers may be used. These retimers implement back-to-back backplane Ethernet PHYs to extend the reach of electrical signals. The ToR switch routes the frames and the optical module converts the medium from electrical to optical by implementing both electrical and optical PHY functions.

Figure 4 illustrates the 400 Gb/s Ethernet PHY from an architectural abstraction level, showing that an 800 Gb/s or 400 Gb/s electrical Ethernet PHY implements:

• Physical Coding Sublayer (PCS) for all required services by the 200GMII/400GMII, such as:
  • DC balancing: PCS implements 64/66-bit line coding and scrambler operations to maintain transition density and DC-balance
  • Transferring encoded data to (from) the Physical Medium Attachment (PMA)
  • Compensating for any rate differences between the 200GMII/400GMII and PMA: Such differences are caused by alignment markers insertion or deletion or due to any rate difference which the PCS corrects by inserting or deleting idle control characters
  • Transcoding from 66-bit blocks to (from) 257-bit blocks
  • Implementing Forward Error Correction (FEC) functions: FEC techniques correct errors at the receiver through coding. These are used to improve link Bit Error Rate (BER). However, coding gain and associated BER improvements come at the cost of increased latency. Considering this trade-off, based on link BER, different FECs can be implemented. Typically for links with BER greater than 10^-5 and less than 10^- 8, Reed Solomon FEC function is used as per the standard. For links where BER is greater than 10^-8 and less than 10^-12, firecode based FEC function is used. Finally, for links with BER less than 10^-12, FEC functions may not be used
  • Adjusting equalizer taps coefficients based on the protocol-defined link training functions are set for backplane applications
• PMA layer adapts to the PCS-formatted signal to an appropriate number of abstract or physical lanes, recovers clock from the received signal and provides various transmit and receive test pattern for local loopback operations
• Physical Medium Dependent (PMD) layer interfaces to the transmission medium, connecting the PHY to the medium which can be many different types of optical or copper cables
• Auto-negotiation layer enables a device to understand the remote-end device’s capabilities and status. Clause 73 of the IEEE Std 802.3 standard defines a new common auto-negotiation protocol which uses the signalling that is independent of the standard speed modes. Auto-negotiation allows devices to advertise and share information, including speed, modes, fault signalling, and other control information

An integrated Ethernet PHY IP that includes the PCS, PMA, PMD and auto negotiation functionality enables faster adoption of the latest 800Gb/s and 400Gb/s Ethernet. Figure 5 shows an example implementation of an 800G/400G PCS.