DDR Hardening Demystified

Introduction

A typical DDR memory interface IP solution includes a DDR PHY and DDR controller, connected using the DFI compliant interface. Each SoC’s performance, floorplan and pad ring requirements are unique, requiring a customizable DDR solution that meets the SoC’s requirements. Optimizing the DDR implementation to meet the SOC design targets and requirements can be challenging as it involves analyzing and fine tuning the design parameters and implementation flow. Using an automated hardening flow to refine the implementation iteratively enables designers to increase productivity and achieve their DDR design objectives. Figure 1 illustrates this automated implementation flow using the Synopsys Galaxy™ Design Platform and Lynx Design System.

Synopsys Professional Services (SPS) offers extensive DDR RTL-to-GDSII design expertise from working closely with Synopsys’ IP developers. Drawing on this experience, SPS has successfully supported dozens of customer SoC DDR hardenings with multiple configurations using Synopsys DesignWare® DDR Memory Interface IP. This article discusses best practices, based on SPS’s experience, to consider for an optimal DDR implementation.

Configuring the DDR

The first step to crafting your DDR solution involves generating the DDR PHY and DDR controller RTL using Synopsys DesignWare DDR PHY Compiler and coreConsultant respectively, as shown in Figure 1. These highly configurable tools and utilities automate the generation of RTL in the context of the SoC.

coreConsultant enables easy configuration of the controller IP and guides the user through implementation and verification as needed. Some of the key parameters, including DDR modes, frequency ratio and memory data width, must be consistent between the DDR PHY and DDR controller. The DDR controller is a highly complex RTL computational block, responsible for interfacing to one or many on-chip busses and organizing memory traffic for improved performance and reduced power via the DFI-compliant interface to the DDR PHY. The DDR controller may be hardened with the DDR PHY or left at the top level. To determine which approach to take, consider the DFI timing and width of the data byte lane. If the DFI interface needs pipeline registers, or the width of the data byte lane is large, hardening the DDR PHY and DDR controller can optimize timing and congestion; otherwise you may leave the controller at the top level. In either case, DFI interoperability between the DDR PHY and controller needs to be maintained.

The DDR PHY Compiler uses a web interface that generates the Verilog model for the DDR PHY. It evaluates more than 60 variables and enables the evaluation of unlimited 'what-if' scenarios. The DDR PHY Compiler also produces an instantly viewable image of the DDR PHY layout, placement scripts, pin list, area and power consumption report, and an RTL model of the PHY.

DDR Hardening

The Synopsys DDR PHY includes PUB logic as soft IP and multiple hard macrocells including an address/command macrocell (AC), an 8-bit data slice macrocell (DATX8), PLLs and SSTL IOs. The AC and DATX8 are custom designed macrocells. As part of the PHY design, Synopsys’ IP developers address the design and timing challenge and package the optimized DDR PHY hard macrocells, eliminating the need for designers integrating the DDR IP to do detailed place-and-route for the high speed timing logic.

Hardening a DDR interface includes placing the hard macrocells and taking the PUB + DDR controller logic through the RTL-to-GDSII design cycle. Figure 2 shows the key considerations for hardening a DDR interface and the flow used for physical implementation using the Galaxy Design Platform.

Floorplanning

Once the DDR PHY has been configured and the SSTL IOs placed, designers must ensure that the bump placement meets the SoC RDL routing requirements and the package rules. DesignWare DDR IP can be partitioned into voltage islands to support multiple power domains and reduce power consumption.

The robustness of the DDR PHY Power Ground (PG) grid needs to be evaluated in context of the whole SoC. In addition to voltage drop and EM analysis, performing signal and power integrity analysis ensures that the DDR PHY has the sufficient minimum number of power and ground pads and on-chip coupling capacitance at the optimal locations. Review the DDR PHY Signal Integrity Report provided by Synopsys to ensure these requirements are met.

Skew Balancing

Besides controlling the clock skew, the signal nets from the DDR PHY macrocells to the IOs also have skew requirements. To alleviate skew, use Galaxy Custom Router’s auto-routing capability for complex high-speed digital and mixed-signal nets. This tool automates the connection of all macrocell (AC, DATX8)-to-IO connections and route signal nets with length and resistance matching.

Keeping the macrocell-to-IO spacing to a minimum will optimize area and minimize the route length. Use shielding to mitigate crosstalk on nets routed adjacent to one another. Slew degradation thru long signal nets and max_capacitance are two other areas that impact design functionality. Slew degradation is best addressed by inserting an equal number of buffers on the macrocell-to-IO routes.

Synthesis

The Synopsys Physical Guidance (SPG) flow is used to synthesize the PUB and DDR controller logic. Depending on the floorplan shape and design goals, clump the PUB logic and assign higher weights to paths between the DFI/PUB and the DATX8 macrocells as shown in Figure 3. This ensures that these paths are given a higher priority during timing optimization. Furthermore, modeling desired ICG clock latencies at this stage creates a better correlated flow.

Placement

Before enabling placement, load the nets routed by Galaxy Custom Router into the synthesized SPG database and apply the desired non-default rules (NDRs) while loading the design into IC Compiler. During placement the path group weights are considered and the DFI logic is placed at the boundary of the DDR controller and PUB, near the DATX8 macrocells as shown in Figure 4.

Clock Tree Synthesis

Clock tree synthesis for all clocks, including the ATPG clock, balances the clocks across multiple scenarios. Select clock buffers with the least delay variation and enable On-Chip-Variation (OCV) clustering as well as OCV path sharing. To minimize crosstalk effects, clocks are typically routed on metal layers above M3.

Routing

All macrocell-to-IO nets and clock nets have already been routed. These pre-routed nets are frozen and NDRs, if any, are maintained. All of the remaining un-routed signal nets in the design are now routed. Then incremental optimizations are done where needed to fix DRC, timing and or crosstalk violations through ECOs based on PrimeTime SI reports.

Conclusion

This article highlights the key DDR hardening issues our Synopsys Professional Services team considers to automate the hardening and integration of a complete DDR solution into an SoC. DesignWare DDR PHY Compiler and coreConsultant provide an automated way to generate the DDR PHY and DDR controller building blocks. DDR PHY design and signoff is achieved using the Synopsys DesignWare Memory Interface IP, Galaxy Design Platform and Lynx Design System.

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