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Introduction
One-time programmable (OTP) non-volatile memory (NVM) is essential for securing and configuring advanced SoC designs across applications targeting high-performance computing, edge IoT, AI, and cloud computing, especially as these technologies migrate to advanced FinFET nodes. OTP memory plays a key role in helping securely storing data, sensitive program code, product information, and encryptions keys for authentication. Spiraling design, mask, and wafer costs in advanced FinFET nodes (Figure 1) make achieving first-pass silicon success more important than ever, with IP reliability being crucial to this goal. Synopsys OTP NVM IP solution, designed for 7nm process and below, ensures secure and reliable operation across Process, Voltage, and Temperature (PVT) conditions, which is mandatory for first-time silicon success.
Figure 1: Escalating mask, wafer and design costs at advanced process nodes
Basic Operation of an Antifuse OTP
An antifuse OTP consists of an array of cells each composed of CMOS transistors. In an antifuse OTP, unprogrammed cells represent a logic value of 0 and programmed cells represent a logic value of 1. When an OTP is first manufactured, all cells are unprogrammed and it is in a logic 0 state. Programming an antifuse OTP involves the application of a high voltage to the locations (cells) that need to be programmed. The high voltage results in a breakdown of the oxide and formation of a channel or filament in it. The filament is essentially a short circuit between the gate and the body of the transistor that forms the cell of the OTP. The presence of the filament allows current to flow between the gate and the body of the transistor, which can be measured. Reading an OTP involves measuring the gate leakage current to determine if a cell is programmed (logic 1) or unprogrammed (logic 0). This process involves using regulated voltages above the core supply voltage to get enough current on the bit lines to reliably read the data.
Reliability Challenges with OTP in Advanced Nodes
Reliable Reads at Operating Voltages
In advanced nodes with thinner oxides, reading at regulated voltages above the core supply voltage makes the OTP more susceptible to leaky bits and misreading bits as logic 1 even when they are not programmed. The thinner oxide layer also causes higher device stress on unprogrammed cells within the word being read.
Ensuring High Programming Yield
Advanced node processes have higher device leakage requiring the use of higher voltages to drive sufficient currents for programming the OTP. However, these higher voltages can result in damaging the devices and lead to programming failures. Due to the thinner oxide layer, advanced node OTP is more susceptible to high voltages and may become over-programmed. Over programming an OTP can result in poor programming quality and unnecessary over-exposure of the cells to high voltage. Additionally, high voltages can cause program disturbs, where unintended neighboring cells are accidentally programmed leading to errors.
PPA Challenges
Higher leakage can also make it very challenging to keep the OTP area competitive and may limit the maximum bit count that can be reliably supported. Another factor in the total cost of manufacturing is programming time. Programming the OTP requires significantly stepping up the voltages, and since supply voltages are lower in advanced nodes, it may take longer to ramp up the voltages to the correct levels needed to drive the programming currents and successfully program the OTP.
Solutions for Reliable Antifuse OTP for Advanced Node Designs
Optimized Bitcell Design
Reliability starts with the bitcell design. The quality of the filament formed during programming depends on how well the oxide is broken, which in turn depends on the bitcell area. If it is too small, breaking the oxide and forming the filament becomes very difficult, leading to programming failures. Conversely, if it is too large, multiple breaks in the oxide may occur during programming. Soft (insufficient) breaks result in incomplete filament formation, while hard breaks create multiple filaments that all conduct current. Soft breaks, being incompletely formed filaments, may not pass enough current. Over time, these may resemble unprogrammed bitcells, rather than programmed ones, a phenomenon known as bake out. Unprogrammed locations in an OTP with larger bitcells may also suffer from higher leakage due to their size, which can affect the array’s clean yield − a measure of how many bits are in a logic 0 state during initial testing after manufacturing. Therefore, the bitcell area must be carefully chosen to optimize the formation of the filament during programming and prevent bake outs, ensuring reliable programmability.
Robust Analog Design of High Voltage Elements
An OTP relies on high voltages for both reading and programming. These voltages are generated and regulated by an Integrated Power Supply (IPS), which is entirely analog in nature. The design of the IPS is critical for the correct functioning of the OTP because variations in the required voltages to establish reliable reads and programming will result in data retention issues or program disturbs.
Analog design is optimized for programming and read paths to achieve hard oxide breaks. Reliable reads over PVT are achieved by detailed design of analog elements.
Data Integrity Signals
The data output from the OTP during reads must always be reliable. Ensuring the integrity of the data read is crucial for determining the overall reliability of the memory. Signals that flag the OTP output as good-to-go are essential to weed out unintended data corruption from voltages that are not stable during the reads.
PPA Optimization in Advanced Nodes
Memory Array and Analog Periphery Design
High device leakage typical of advanced node processes requires intervention to ensure not only reliability but also that performance and power targets are met for the OTP. The length of the bitlines and the width of the memory array must be carefully designed to avoid excessive IR drop when the memory is operating. Additionally, managing leakage power is crucial. By carefully designing both the memory array and the analog periphery it is possible to meet the SoC requirements.
Optimized Analog Design
The sense-amplifiers, which sense and determine the value of accessed locations in an OTP, must be particularly sensitive to the low voltages typical of advanced nodes because the current coming out of these bit cells is way lower than in preceding FinFET nodes. Programming speed, which impacts manufacturing cost, needs to be optimized through expert design of the high-voltage circuitry. Achieving this is challenging due to conflicting requirements: the need to minimize the overall area of the OTP while still providing enough current from the charge pump in the IPS to successfully program the memory.
Synopsys OTP NVM IP for Advanced Nodes
Designed for Reliability
Synopsys OTP NVM IP for advanced nodes started with the design of a robust, optimized antifuse bit cell (Figure 2). High Temperature Operating Life (HTOL) tests show no shifts in bit cell currents at different read-points, demonstrating its reliability across PVT conditions. Synopsys has optimized the bit cell area for proper oxide breakdown ensuring successful programmability, high programming performance, and excellent array clean yield.
Figure 2: Synopsys OTP NVM bit cells optimized for antifuse formation
The Synopsys OTP NVM IP solution (Figure 3) includes of a memory array composed of tiled bit cells, decoders, analog components such as sense amplifiers, and an IPS that generates the necessary voltages for reads and programming. Extensive care has been taken to design the OTP array to minimize leakage at advanced nodes. Synopsys’ choice of read voltage ensures reliable bit cell reads and guarantees data retention for at least 10 years. The programming voltage and algorithm are designed to prevent unintentional program disturbs. Output pins on the OTP help ensure data is not read prematurely providing confidence in data integrity.
Figure 3: Synopsys OTP NVM IP for advanced nodes
The Synopsys OTP NVM IP is further enhanced with additional bits to insure against random manufacturing defects and field failures. Each word is equipped to correct a leaky bit and/or a programming failure during initial testing. Additional repair resources are available for multiple failures within a word, and entire words can be replaced if necessary. The OTP memory array also includes additional bits for storing Error Correction Codes (ECC).
Cost Effective
Synopsys OTP NVM IP is available in a wide range of configurations, enabling designers to select the optimum option for their SoC. It is area-optimized to reduce silicon costs and features fast programming capabilities to minimize production costs.
Easy to Integrate
A controller that interacts with the Synopsys OTP NVM and manages the reads and writes, test-and-repair, and ECC encoding and decoding is part of the overall OTP solution. The controller is delivered as soft IP in the form of RTL, with the OTP memory array and IPS integrated into a single hard macro. To further ease integration into the SoC, the OTP solution also supports standard APB interfaces. Additionally, the OTP supports the standard JTAG 1149.1 interface to facilitate testing. The necessary synthesis scripts and constraint files are included in the deliverables to help the end user harden the OTP controller in their design.
Advanced Security Architecture
Given the critical role of OTP in advanced nodes for security, Synopsys has implemented robust features to enhance protection. Each word has both read and write locks, along with macro and sector-level locks. Programming and testing the OTP are conducted through a secure APB interface, which can be locked from user access once these processes are complete.
The OTP supports a low power mode that turns off the memory array and IPS when not in use, making it difficult to electrically snoop and reverse engineer the stored data or code. Data obfuscation is made possible with the ability to program all unprogrammed locations if a hacking attempt is detected, effectively disabling the embedded OTP.
A safe boot feature implemented by the controller, ensures that the OTP wakes up in a locked state, requiring explicit user action to change it to a readable state. Additionally, the OTP can be configured in a differential read mode, making it challenging for hackers to determine the power signature based on the stored values.
Conclusion
In advanced FinFET nodes, OTP is essential to configuring and securing SoCs. Using anything less than the most reliable OTP IP available on the market can result in failed silicon and catastrophic consequences for product launch and market share. Synopsys OTP NVM IP has been designed from the ground up to be highly reliable, PPA optimized, and secure. It offers a complete solution, including a controller to ease integration into the target design. Synopsys OTP NVM IP is silicon-proven, and available for 7nm and smaller process nodes.
For more information, visit Synopsys NVM IP.
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