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Synopsys Sessions & Presentations
Best of Both Worlds: Bridging the Gaps in Engineering Software for Semiconductors and Systems
Presenter: Shankar Krishnamoorthy
Type: DAC Pavilion Panel
Time: 11:15am - 12:00pm PDT
Location: DAC Pavilion, Level 2 Exhibit Hall
Synopsys Cloud and AWS: Unleashing the Power of AI and Cloud to Accelerate Your Chip Design
Speaker: Archana Varanasi
Type: Synopsys Partner Booth Session
Time: 11:30am - 12:00pm PDT
Location: AWS' Booth Theater
Synopsys & Intel Foundry Accelerate Advanced Chip Designs
Speaker: Bob Hwang
Type: Synopsys Partner Booth Session
Time: 1:00pm - 1:20pm PDT
Location: Intel Foundry Booth #2337
How to Write RISC-V PSS Models to Enable Generating Verification Scenarios for RISC-V Platforms
Authors: Sandeep Mehrotra, Hillel Miller
Type: Tutorial
Time: 1:30pm - 5:00pm PDT
Location: 3001, 3rd Floor
Synopsys Cloud and Azure: Unleashing the Power of AI and Cloud to Accelerate Your Chip Design
Speaker: Swathi Rangarajan
Type: Synopsys Partner Booth Session
Time: 2:00pm - 2:30pm PDT
Location: Microsoft's Booth Theater
Breaking the Formal Convergence Barriers of a Floating-Point Dot-Product Block for AI/ML Accelerators
Presenters: Neelabja Dutta, Ashish Kapoor, Reily Jacoby
Type: Front-End Design
Time: 2:15pm - 2:30pm PDT
Location: 2010, 2nd Floor
Time: 3:00pm – 3:45pm PDT
Location: DAC Pavilion, Level 2 Exhibit Hall
Time: 3:30 p.m. - 5:00 p.m. PDT
Location: 2010, 2nd Floor
History, Present, and Future of STA: A Travel through Timing
Organizer: Sabya Das
Presenter: Peivand Tehrani
Type: Back-End Design
Time: 3:30pm - 5:00pm PDT
Location: 2008, 2nd Floor
Time: 3:30pm - 5:00pm PDT
Location: 2012, 2nd Floor
Advanced LLE Aware Timing Signoff Methodology
Authors: Ahmed Shebaita, Sangwoo Han, Tajendra Singh, Li Ding, Sunik Heo
Type: Engineering Track Poster
Time: 5:00pm - 6:00pm PDT
Location: Level 2 Exhibit Hall
Programmable IO Ring Builder and Checker
Authors: Manoj Kumar, Anurag Mittal, Praveen Jakki, Avinash Gupta, Priyanshi Jain, Priyanka Goel
Type: Engineering Track Poster
Time: 5:00pm - 6:00pm PDT
Location: Level 2 Exhibit Hall
Shift Left Solution for Enhancing Power Integrity in Physical Design Construction with RedHawk-Fusion
Author: Jin Wang
Type: Engineering Track Poster
Time: 5:00pm - 6:00pm PDT
Location: Level 2 Exhibit Hall
Architecting a True Hybrid Cloud Environment for Massively Parallelized EDA Workloads
Authors: Sridhar Panchapakesan, Vikram Bhatia
Type: Exhibitor Forum
Time: 10:30am - 11:00am PDT
Location: Exhibitor Forum, Level 1 Exhibit Hall
Quantum Computing: Accomplishments, Bottlenecks, and Timelines
Author: Jamil Kawa
Type: Research Panel
Time: 10:30am - 12:00pm PDT
Location: 3014, 3rd Floor
Advanced in Silicon Lifecycle Management & Test
Session Chair: Jon Colburn
Type: Research Manuscript
Time: 10:30am - 12:00pm PDT
Location: 3010, 3rd Floor
Considering Selective Resistance Extraction for Performance & Accuracy Trade-off for Memory IP Simulation
Presenters: Vartul Sharma, Rakesh Shenoy
Type: IP
Time: 10:45am - 11:00am PDT
Location: 2010, 2nd Floor
Fast and Deterministic Memory Yield Estimation using Machine Learning Augmented Statistical Simulations
Presenter: Rakesh Shenoy
Type: IP
Time: 11:00am - 11:15am PDT
Location: 2010, 2nd Floor
Enabling Low-Risk SoCs with Synopsys IP for Intel Advanced Processes
Speaker: Ravi Todi
Type: Synopsys Partner Booth Session
Time: 11:20am - 11:40 am PDT
Location: Intel Foundry Booth #2337
The Next Step to Efficient AI: Number Formats, Quantization, and Beyond
Session Chair: Igor Markov
Type: Research Manuscript
Time: 1:30pm - 3:00pm PDT
Location: 3001, 3rd Floor
Advanced Logic Synthesis - Improving Runtime and Quality
Session Chair: Sabya Das
Type: Research Manuscript
Time: 1:30pm - 3:00pm PDT
Location: 3004, 3rd Floor
Time: 1:30pm - 3:00pm PDT
Location: 3008, 3rd Floor
Silicon.da: The First Integrated and Cloud-Ready Silicon Lifecycle Management Analytics Solution from Design Through Manufacturing
Speaker: Guy Cortez
Type: Synopsys Partner Booth Session
Time: 2:00pm - 2:15pm PDT
Location: AWS' Booth Theater
Automated Design Scenario Extraction from a Large Design for Faster Debug of Static Verification Tools
Presenters: Gaurav Pratap, Vishal Keswani, Sachin Bansal, Amit Goldie, Sanjay Gulati
Type: IP
Time: 2:00pm - 2:15pm PDT
Location: 2012, 2nd Floor
Enabling Protocol Validation of High Speed Serial Links using SerDes to Transfer Data Between PHY Chip and Link Layer on FPGA
Presenters: Priyanka Goel, Aashish Bhide, Vivek Uppal, Ameer Youssef, Nitin Sharma
Type: IP
Time: 2:45pm - 3:00pm PDT
Location: 2012, 2nd Floor
Demystifying Failure Mechanisms at Advanced Nodes
Organizer/Presenter: Pawini Mahajan
Presenter: Yervant Zorian
Type: IP
Time: 3:30pm - 5:00pm PDT
Location: 2012, 2nd Floor
Time: 3:30pm - 5:00pm PDT
Location: 2008, 2nd Floor
What is the Future of Design Verification? UVM, PSS, Formal, VIP, AI & Beyond
Presenter: Arturo Salz
Type: Front-End Design
Time: 3:30pm - 5:00pm PDT
Location: 2010, 2nd Floor
Generative AI for Chip Design: Game Changer or Damp Squib?
Author: Stelois Diamantidis
Type: Research Panel
Time: 3:30pm - 5:30pm PDT
Location: 3014, 3rd Floor
Dashboard Model for Foundry Early Node Assessments using Synopsys Design.da
Authors: Luna Kang, Jayson Seo, Ann-Woo Lee, James Ban
Type: Engineering Track Poster
Time: 5:00pm - 5:00pm PDT
Location: Level 2 Exhibit Hall
Time: 5:12pm - 5:13pm PDT
Location: Level 2 Exhibit Hall
Virtual Instrumentation-based Predictive Checks for Shift Left Low Power Verification
Authors: Sachin Bansal, Yi Liu, Vijay Poosa, M. Vaishnavi Reddy, Nupur Gupta, Vishal Keswani, Amit Goldie, Manish Goel
Type: Engineering Track Poster
Time: 5:45pm - 5:46pm PDT
Location: Level 2 Exhibit Hall
Avoiding CDC Bugs Introduced during Synthesis Optimizations and Netlist Transformations
Authors: Suresh Barla, Paras Mal Jain, Gunjan Mamania, Kenneth Trejos
Type: Engineering Track Poster
Time: 5:48pm - 5:48pm PDT
Location: Level 2 Exhibit Hall
Heterogeneous 3DIC Multi Voltage Timing Signoff
Author: Santosh Varanasi
Type: Engineering Track Poster
Time: 5:51pm - 5:52pm PDT
Location: Level 2 Exhibit Hall
Automated Constraint Promotion Methodology from IP to SoC for Complex Designs
Authors: Mallik Devulapalli, Rimpy Chugh
Type: Engineering Track Poster
Time: 5:58pm - 5:59pm PDT
Location: Level 2 Exhibit Hall
AI Paradigms Beyond Deep Neural Networks
Session Chair: Parivesh Choudhary
Type: Research Manuscript
Time: 10:30am - 12:00pm PDT
Location: 3001, 3rd Floor
Shift Left Detection and Root Cause Analysis of Synthesis Optimized Registers at RTL Level
Presenters: Kartik Agarwal, Himanshu Kathuria, Jaskaran Ajimal, Amil Jalota, Harsha Somashekar
Type: Front-End Design
Time: 11:24am - 11:42am PDT
Location: 2010, 2nd Floor
Design Constraint Strategy for Dealing with Cascaded Clock MUX Structures
Presenters: Anish Keshava, Aakarshak Nandwani, Nitesh S, Satyanarayana Patnala, Sridharr S
Type: Front-End Design
Time: 11:42am - 12:00pm PDT
Location: 2010, 2nd Floor
Design Automation Advancement in the Analog Domain
Organizer: Sabya Das
Presenter: Vuk Borich
Type: Back-End Design
Time: 1:30pm - 3:00pm PDT
Location: 2008, 2nd Floor
Power Your Future: Investments for the Chip Design Workforce and Research
Organizers: Angela Hwang, Patrick Haspel
Author: Joe Cole
Type: Research Panel
Time: 1:30pm - 3:00pm PDT
Location: 3014, 3rd Floor
CDC Multimode Signoff Methodology
Presenters: Navneet Chaurasia, Amit Goldie, Deepak Ahuja, Sanjeev Chaudhri, Paras Mal Jain
Type: IP
Time: 1:48pm - 2:06pm PDT
Location: 2012, 2nd Floor
Invited: HDL-GPT: High Quality HDL is all you Need
Author: Ganapathy Parthasarathy
Type: Special Session (Research)
Time: 2:00pm - 2:30pm PDT
Location: 3006, 3rd Floor
Time: 3:30pm - 5:30pm PDT
Location: 3014, 3rd Floor
Voroni Diagram-based Multiple Power Plane Generation on Redistribution Layers in 3D Ics
Authors: I-Te Lin, Ho-Chieh Hsu, Chia-Ming Liu
Type: Research Manuscript
Time: 4:45pm - 5:00pm PDT
Location: 3008, 3rd Floor
Late Breaking Results: On the One-Key Premise of Logic Locking
Authors: Yinghua Hu, Hari Cherupalli, Mike Borza, Deepak Sherlekar
Type: Late Breaking Results Poster
Time: 6:00pm - 7:00pm PDT
Location: Level 2 Lobby
Attacks and Defenses at Microarchitecture Level and Beyond
Session Chair: Yinghua Hu
Type: Research Manuscript
Time: 10:30am - 12:00pm PDT
Location: 3008, 3rd Floor
