Synopsys Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial →
Extraction Continuum
Faster Collateral Generation & Tighter Correlation Between Tools
Covering Each Stage of the Design Technology Co-optimization (DTCO)
Design Technology Co-optimization (DTCO) has 3 major stages as shown in figure 1, Technology Development, Design Enablement, and IC Design, with each stage needing different extraction tools. On top of that, each stage of DTCO is performed by different groups in a foundry or IDM, many times in a silo. This results in inefficiencies and additional validation work when the output of one group is passed on to another group. Each group manually creates collateral for their tools and correlates the output of the tools with other groups. The Extraction Continuum provides an automated flow that provides a seamless crossover from one tool to another making the DTCO chain more efficient, thereby enabling more efficient design experiments and faster PPA evaluations.
Figure 1: DTCO stages
The Typical Application Flow for Extraction Continuum
A typical application flow for extraction continuum is shown in figure 2. Each extraction tool is suited for a DTCO stage. Tech files for each tool originate from same source (Process Explorer) and they are correlated against each other, resulting in correlation by construction flow.
Figure 2: Extraction Continuum Typical Applications
Synopsys Solutions
Synopsys has tools to cover the entire extraction continuum as shown in Figure 3 with each tool trading off accuracy vs performance/capacity. There is an automated flow in place as shown in Figure 4 to generate tech files for each of the tools resulting in faster collateral generation & tighter correlation between the tools.
Figure 3: Spectrum of extraction tools to support the continuum
Figure 4: Auto-generation of Tech files for Raphael FX, QuickCap NX, Rapid3D from Process Explorer
Raphael FX
Raphael is the gold standard, 2D and 3D resistance, capacitance, and inductance extraction tool for optimizing on-chip parasitic for multi-level interconnect structures in small cells. As a reference field solver, Raphael provides the most accurate parasitic models in the industry. Trusted by major foundries, interconnect parasitics generated by Raphael are included as part of their design reference guide.
QuickCap NX
QuickCap NX is the golden extraction reference tool based on high accuracy 3D Field Solver which is well suited for advanced 14nm FinFET and beyond process technologies. Embedded 3D device visualizer makes it ideal for process exploration. High accuracy extraction, reference tool to rule based extractor, standard cell characterization, memory cell characterization and enhancing PDK quality are some of the key applications served by QuickCap NX.
StarRC
StarRC™ solution is the EDA industry’s gold standard for parasitic extraction. A key component of Synopsys Design Platform, it provides a silicon accurate and high-performance extraction solution for SoC, custom digital, analog/mixed-signal. memory IC and 3DIC designs. StarRC offers modeling of physical effects for advanced process technologies, including FinFET technologies at 16 nm, 14 nm, 10 nm, 7 nm, 5 nm and beyond. Its seamless integration with industry-standard digital and custom implementation systems, timing, signal integrity, power, physical verification, and circuit simulation flows along with debugging capability delivers unmatched ease-of-use and productivity to speed design closure and signoff verification. StarRC comes with an in-built field solver Rapid3D™, which can serve as a reference or provide higher accuracy measurements. 2.5D and 3D-IC extraction is also supported by StarRC.