Advancing IC Design and Test Automation: A Discussion with Deirdre Hanford on DARPA AISS Program

Q: How will you achieve that?

AISS touches many phases and processes in the IC design lifecycle, from creation, intake and integration of IP for specific functions, to tools to integrate and validate a design, and on through to the fab, testing and packaging of finished ICs. At every stage, checks are done to ensure that the design is what was specified, vulnerabilities like trojans and backdoors are not present, and so on. Protections are added so that the provenance of the product can be assured, and in some cases, the full functionality is not available until an unlocking key is supplied. This happens by extending the capabilities of the design and verification tools, providing workflows that authenticate design inputs, transformations and that only the authorized users of those tools have access to them. Three different business units in Synopsys - Design Group, Solutions Group and Verification Group -  are cooperating to make this happen, in addition to six subcontractors in our team: ARM, Boeing, UltraSoC, UC San Diego, University of Florida, and Texas A&M University.  

Q: Please tell us more about your Partners, and why were they chosen?

As mentioned earlier, the Synopsys team includes six partners. Boeing is unquestionably one of the premier aerospace companies in the world and a key supplier to the US government. They are providing an aerospace-oriented reference design on which we'll be testing the technologies and methods developed in AISS. ARM is a top provider of processor technology used in aerospace and defense embedded systems and was a natural fit for the program. UltraSOC was chosen for its system-level introspection technology that will be key to building chips that are capable of supervising their own operations to look for signs of impending attacks. This brings us to our academic partners. Florida Institute for Cybersecurity (FICS) Research at the University of Florida brings deep expertise in a range of hardware security topics from physical and reverse-engineering attacks to threat heuristics, logic locking and design hardening and provenance. Texas A&M will provide logic obfuscation technology and brings with them experts from the University of Texas at Dallas and New York University.  University of California at San Diego is providing advanced system interconnect technology and includes contributors from Purdue University. We're extremely happy to be working with such a great group of industrial and academic partners.

Q: What else is novel about the program?

It almost goes unnoticed in the program, but the entire engineering environment including EDA tools, IP repositories and security tools is based in the cloud. The environment incorporates features to enable very fine-grained access controls and identity that provides a lot of the capabilities for proving design inputs provenance and traceability of work products as designs move through the workflow that transforms a high-level design into a manufacturable set of masks for the fab to manufacture and tracks wafers and chips through the test and packaging processes.  A cloud management infrastructure ultimately tracks chips from manufacturing to integration in systems, throughout their deployment life and finally to end of life. This is a very sophisticated view of the microelectronics lifecycle that goes well beyond usual commercial product flows. All of the Performers in the program will contribute to the development of this environment and the infrastructure to enable it. 

Q: Any last thoughts?

We are excited to have been selected to lead the AISS program, and are now working full speed ahead to deliver on this challenging and visionary view of microelectronics. Check back here from time to time to see how we're progressing.