VC SpyGlass IDC Datasheet

With increasing complexity and growing chip sizes, verifying the correctness of register optimization is a challenge. Implementation or synthesis solutions available in the industry lack the ability to backtrace to the problematic RTL or constraints causing register optimizations. Any unintended register optimizations observed on the design may seep into silicon leading to costly respins. Furthermore, the impact of unintended optimization can become severe for implementation engineers when the area realized during implementation increases significantly from one iteration to another forcing them to start the whole implementation process over again to meet the area targets. Synopsys VC SpyGlass™ Implementation Design Checks (IDC) provides a comprehensive methodology for flagging the registers early at the RTL stage with high debug productivity instead of during synthesis, thereby enabling a predictable overall design cycle. 

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