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DVCon 2019 Verification Lunch Panel
Industry Leaders
Verify with Synopsys
On February 28, 2019 Synopsys hosted a verification panel at DVCon. Ramesh Dewangan (Synopsys) delivered an update on the next wave of verification innovation in Synopsys’ Verification Family, highlighting new solutions for ZeBu Server 4, HAPS-80 Desktop Prototyping, and VC Formal Regression Mode Accelerator App.
Eamonn Quigley (Arm) spoke about the verification challenge of complex IC development and how the Synopsys HAPS FPGA-based prototyping solution is a fundamental piece of the verification strategy for all Arm IP products. Amol Bhinge (NXP) shared his insights on the exploding complexity of verification challenges, which remain in the critical path of time to market.
Speakers
Ramesh Dewangan
Synopsys Verification Update
Senior Director of Marketing, Verification Group, Synopsys
Eamonn Quigley
FPGA-based Accelerated IP Verification at Arm
FPGA Engineering Manager, Arm
Amol Bhinge
Design Verification: Networking and Automotive
R&D Emulation and Verification Hardware Director, NXP
