Enabling High-Quality, Easily Maintained RISC-V Processor Models

RISC-V processors have become very popular in recent years, and fast, high-quality models lie at the heart of developing both processors and the SoCs that contain them. This white paper focuses on one critical component of the RISC-V ecosystem: fast, high-quality processor models for a range of use cases including processor verification. With the range of use cases, and the ability to customize the RISC-V processor, ease of maintenance and extendibility of the model are two key requirements. After outlining the key requirements for these models, this paper discusses the use of the open standard Open Virtual Platforms (OVP) application programming interfaces (APIs) used in C/C++ for building high performance processor models, including those available for RISC-V from Synopsys.

Key Takeaways:

• RISC-V processor models are needed for a wide variety of use cases.
• RISC-V process models must be able to interface with simulators, support software debug and analysis tools, and link architecture exploration tools.
• The Synopsys ImperasFPM RISC-V processor models support all of these use cases and have the ability to be extended with custom instructions and control and status registers.
• The OVP APIs used in the ImperasFPM RISC-V processor models provide multiple benefits including quality, flexibility, extensibility, high performance, and ease of documentation, while reducing the resources required for processor development and maintenance.
• These benefits have been proven with results from hundreds of projects, including more than thirty tapeouts enabled by processor verification using ImperasFPM.