Cloud native EDA tools & pre-optimized hardware platforms
Date: May 20, 2025 | 7:00 AM PST
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The successful switch from 4 to 5G required rethinking important architectural concepts in wireless SoCs. The traditional split between general-purpose programmable processors (primarily for MAC and higher-level protocols) and hardwired datapaths (primarily for digital front-end and baseband processing) no longer holds. Designers bring into play Application-Specific Processors (ASIPs), to meet 5G's high data rates and low latency requirements with low power consumption, while maintaining software programmability to quickly adapt to and deploy new functionality. 5G SoCs may contain a multicore ASIP configuration, with different ASIPs customized to implement specific parts of the 5G block diagram, such as FFT, channel estimation and equalization, interleaving, or channel coding. The individual ASIPs may exhibits high amounts of instruction-level and data-level (SIMD) parallelism with specialization of functional units and memory architecture.
Synopsys' ASIP Designer tool enables customers to explore, design and optimize differentiating ASIP architectures for 5G and beyond in very short time, in both mobile systems and base stations.