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The ability to mix and match multiple ISA extensions and add user-defined ISA extensions makes RISC-V verification more challenging than conventional processor verification. This Synopsys webinar demonstrates the verification of standard RISC-V ISA extensions. A subsequent webcast will demonstrate custom ISA verification. The multiple ISA verification problem is solved by RISCV-DV with configurability for ISA specific test generation. RISCV-DV addresses the generation of ISA specific tests in one pass of simulation using Synopsys VCS® as the efficient constraint solver for instruction generation using constraint random methodology. The tests consist of valid instruction sequences (programs) for the target ISA of the processor core under verification. The generated programs are run on the Bluespec processor core simulated with Synopsys VCS and the results are compared with Spike instruction set simulation (ISS) results.
This presentation will showcase:
- A reference methodology for verifying a Bluespec RV32IMC MCU-X processor core based on RISCV-DV.
- How designers can leverage Synopsys VCS simulation and Synopsys Verdi® for debug and relevant advanced coverage methodology, to help speed verification signoff.
- The combination of RISCV-DV and Synopsys tools provides a powerful and flexible solution for RISC-V verification and highest coverage.
- Demo on the RISC-V verification solution on the Synopsys Cloud platform.
Whether you are a chip verification architect or a verification engineer or a system designer, this Synopsys webinar will provide valuable insights into how to set up a constraint random verification solution for a RISC-V processor to achieve the highest coverage.
Speakers
Bipul Talukdar
Senior Director, Applications Engineering
Bluespec
Bipul Talukdar is Senior Director of Applications Engineering for Bluespec Inc. He is an expert in hardware functional verification with a specialty in verification IP (VIP) development, formal property verification, and hardware emulation. He leads Application Engineering and Support for Bluespec. Bipul has a strong background in formal verification of RISC-V based cores/subsystems, arm based cores/subsystems and coverage-based closure. His previous engineering roles at SiFive, Cadence, Mentor Graphics (Siemens) and SmartDV Technologies give him a broad perspective on the myriad challenges faced by design and verification teams, allowing him to partner with customers for success throughout product evaluations and deployment. Bipul holds a Bachelor of Science in Engineering, Electronics, and Telecommunication from India’s National Institute of Technology, Silchar. He is based in San Jose, California.
Prabha Krishnaswami
Applications Engineer, Senior Staff
Synopsys
Prabha Krishnaswami is an Application Engineer at Synopsys, focusing on VCS and Verdi products. She also collaborates with the global RISC-V customers to showcase the Synopsys RISC-V solution. She has a background in design and verification with expertise in SoCs and subsystems. Prabha likes music, reading and enjoys long walks.