Industry Panel: Optimizing Memory in Multi-Die Architectures

Multi-die designs have emerged as the next big disruption in computing to cater to the unsatiable need for larger, faster, and more energy efficient compute systems. For such high-performance computing systems there is a need for memories to perform at peak levels, while optimizing power, performance, area, and cost.

Watch this panel to hear Ansys, Micron, Synopsys, and Western Digital discuss:

• The different memory chip design and verification approaches for multi-die designs
• The use of HBM and other memory technologies in 2.5 and 3D packaging