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Synopsys Webinar | Available on Demand
As traditional Moore’s law scaling approaches its physical limits, the industry is moving towards multi-die solutions for higher electronics system densities. Multi-die designs present one way for engineers to pack more functionality into silicon chips and improve yield without affecting fabrication feasibility or project budgets.
The Universal Chiplet Interconnect Express (UCIe) standard was introduced in March of 2022 to help standardize die-to-die connectivity in multi-die systems. UCIe can streamline interoperability between dies on different process technologies from various suppliers. However, multi-die system’s complexity drives the need for a high quality verification process by utilizing Protocol verification IPs and hardware-based verification solutions to achieve great levels of quality in SoCs.
This Synopsys webinar explains various multi-die design types, UCIe multi-die design verification challenges, and how Synopsys verification solutions helps in overcoming these challenges.
Speakers
Varun Agrawal
Senior Staff, Product Manager
Synopsys
Varun Agrawal is a Product Manager for VIP, Virtual System Adaptors and Protocol Solutions for Hardware Assisted Platforms, System Design Group, at Synopsys.
Varun has 15 years of experience in IP to system level functional verification with expertise in simulation, emulation and virtualization domain. Prior to Product Management, Varun led R&D projects in virtualization and emulation, and worked in various development and customer facing roles at multiple design and EDA companies. He holds Bachelors in Electronics and Communication from NIT Hamirpur, India, and MBA in International Marketing from India Institute of Foreign Trade (IIFT), New Delhi, India.
Narasimha Babu GVL
Scientist
Synopsys
Narasimha Babu GVL is a Synopsys Scientist with 18+ years of experience providing protocol verification solutions for a variety of standard protocols including Ethernet, AMBA, MIPI, UFS, PCIe, CXL and UCIe.
Babu is a primary Synopsys representative for the Compute Express Link (CXL) Compliance Work Group and part of the DVCon India steering committee. He is also actively involved in writing and editing technical blog publications on Protocol verification.