Verifying AI Designs - Solving the Challenge of Quadrillions of Verification Cycles

Date: Wednesday, April 9^th 10:00am – 11:00am PDT

Today’s AI designs stress verification teams to an unprecedented extent. The compound complexity from software, hardware, interfaces, and architecture options leads to the challenge of running quadrillions of verification cycles across IP, sub-systems, SoCs, and Multi-die designs. Learn how leaders from AMD, Arm, Nvidia, and others address these challenges with Synopsys’ latest family of Hardware-Assisted Verification products, modularity of verification, and mixed-fidelity execution setups using virtual prototyping, emulation, and FPGA-based prototyping.

Why You Should Attend:

• Expert Insights: Gain valuable knowledge from industry leaders at AMD, Arm, and Nvidia as they share their strategies for tackling the complexities of AI design verification.
• Advanced Solutions: Learn about the latest Synopsys Hardware Assisted Verification products, ZeBu-200 and HAPS-200, and how their modularity and mixed-fidelity execution setups can streamline your verification processes.
• Comprehensive Techniques: Discover how to efficiently manage quadrillions of verification cycles using cutting-edge methods like virtual prototyping, emulation, and FPGA-based prototyping for IP, sub-systems, SoCs, and Multi-die designs.