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Table of Contents
Originally published October, 2023
Overview
Arm® recently announced the availability of the next version of the Arm® AMBA® 5 AXI Protocol Specification, AXI Issue K (AXI-K). This blog will explain some of the feature updates of the AMBA AXI-K specification:
- Memory Encryption Contexts (MEC), related to Realm Management Extensions (RME) that is part of AXI-J specification
- Additional updates:
- An additional option to extend the Memory Partitioning and Performance Monitoring (MPAM) Partition ID (PARTID) field to 12-bit
- An additional option for ‘simplified’ Memory Tagging Extension (MTE)
- Provision to disable fixed type bursts
- An option to relax ordering requirements between Device and normal non-cacheable requests
- Issuing WriteNoSnpFull opcode without using shareable cache lines
Let us look at these features in detail
What are Memory Encryption Contexts (MEC)?
In our previous blog on AXI-J, we talked about Arm's Realm Management Extension (RME) which is part of Confidential Compute Architecture (CCA), under Arm v9 architecture. RME provides a set of features for creating and managing isolated execution environments called Realms. Memory Encryption Contexts (MECs) extensions to RME allow each Realm to have its own unique encryption context. This feature plays a key role in assigning MECs to all memory accesses within the Realm Physical Address Space. All memory transactions are associated with a MECID, which is used by the Memory Encryption Engine as an index into a table of encryption contexts, that contributes to the external memory encryption. So, each set of Realm data can be encrypted in a different way. This means, that a malicious agent that has access to the physical memory device and can decipher one set of Realm data, cannot use the same decryption method to access other sets of Realm data. So, overall, MEC plays a key role in the confidential computing of the data.
In the AXI-K specification, this feature can be enabled only when RME is enabled. This feature is applicable for AXI5, ACE5-Lite, and ACE5-Lite DVM interfaces. The signals AWMECID, and ARMECID on write and read request channels are required to support the MEC to carry the corresponding MECID value. The width of these signals, when present, must be 16.
Additional Updates
MPAM Part ID Extension:
Memory Partition and Performance Monitoring (MPAM) defines independent partition ID (PARTID) spaces for each Physical Address Space (PAS). In addition to the existing 9-bit PARTID, AXI-K specification provides an option to have a 12-bit MPAM PARTID.
‘Simplified’ MTE Support:
For Memory Tagging Extensions (MTE) support, in addition to existing ‘Basic’ and ‘Standard’ options, a new option ‘Simplified’ is introduced. This new option can be used by the components that can support the reading and writing of the tags, but not the tag operation or partial tag updates.
Disable Fixed Bursts:
The use case of AXI Fixed burst is to access FIFO-like components, which is not commonly used. The AXI-K specification provides an option to disable the fixed type burst requests.
Relaxed Ordering Requirements:
AXI-K specification also introduces an option to relax the ordering requirements between Device and Normal non-cacheable requests with the same ID to the same location.
Synopsys end-to-end protocol verification solutions for AMBA AXI5, AXI5-Lite, ACE5, ACE5-Lite, ACE5-Lite/DVM, CHI-F provide performance analysis and comprehensive system-level debug capabilities to check for functional correctness, data integrity, and cache coherency. In-built sequence collection, functional coverage model, verification plans, and usage examples are included to ensure fast bring-up and achieve wholistic verification closure. Synopsys is collaborating with early customers and partners to extend the standard architecture for their next generation designs with new features available now with latest specifications.
Synopsys VIP is natively integrated with the Synopsys Verdi® Protocol Analyzer debug solution as well as Synopsys Verdi® Performance Analyzer. Running system-level payload on SoCs requires a faster hardware-based pre-silicon solution. Synopsys transactors, memory models, hybrid and virtual solutions based on Synopsys IP enable various verification and validation use-cases on the industry’s fastest verification hardware, Synopsys ZeBu® emulation and Synopsys HAPS® prototyping systems.
More information on Synopsys AMBA VIP and test suites is available at synopsys.com/vip
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