Deciphering the New TileLink Standard

Increasing complexities of processor architectures with limited overall performance scale-up have created a demand for a domain specific architecture to ensure extensive performance scaling. – this is when RISC-V began to gain momentum. RISC-V is gathering widespread attention throughout sectors like datacenter accelerators, mobile & wireless, IoT, etc. for its extensibility. Many industry leaders are beginning to adopt RISC-V for its open source availability that reduces time-to-market and cost effectiveness while at the same time scaling up the overall performance and leaving room for innovation and automation.

TileLink is an open standard chip-scale interconnect designed to be used with RISC-V processors. It also supports other ISAs.

TileLink is an easy to implement cache-coherent bus protocol that can be utilized in a System-on-Chip (SoC) to connect accelerators, general purpose multiprocessors, co-processors, DMA engines and simple or complex designs.

Wonder what TileLink has in store?

• Fast-scalable interconnect providing low latency and high throughput
• Physically addressed, shared memory subsystem that may be implemented over scalable, hierarchically composable, point-to-point networks
• Multiple layered cache coherent access for both caching or non-caching masters used together in a system

Key features of TileLink:

• Designed for verifiable deadlock freedom (for any conforming SoC)
• Improved throughput by supporting out-of-order completion of concurrent operations
• Progressive conformance level complexity
• Address space-based properties
• Physically independent channels

TileLink follows a Directed Acyclic Graph (DAG) topology where agents are vertices and links are edges directed from Primary to Secondary interfaces. Each link consists of a set of 2 mandatory channels (channel A & D) and 3 optional channels (channel B, C & E required for TL-C). To ensure deadlock freedom, TileLink specifies a prioritization among channels to be followed strictly:

A << B << C << D << E is the order of increasing priority levels for channels A, B, C, D and E.

Requests are always initiated by Primary on request channel and it then waits for a response from secondary on response channel.

Three conformance levels

TileLink may support operations such as Put, Get, Atomic, Hint, Acquire, Probe & Release based on the 3 conformance levels TL-UL, TL-UH & TL-C.