SNUG Austin Call for Content

SNUG brings together more than 2000 Synopsys users, technologists and industry experts for Silicon Valley's largest technical conference devoted to the challenges of electronic design and verification. As a published SNUG author and presenter, you will increase your visibility in the local design and worldwide Synopsys user communities. In addition to the professional recognition, you will be eligible for significant cash awards (please check your company’s gift acceptance policy).

The call for content is open March 10, 2020 - April 21, 2020. The SNUG Technical Committee will review the submitted proposals and notify authors about program acceptance by May 6, 2020. 

We have a preliminary list of topics to get you started, but don’t let that limit your ideas or innovation in your submission:

AI and Machine Learning

• Improving productivity and achieving faster QoR closure with machine learning in the Synopsys design flow
• From the data center to the edge – enabling highest performance AI designs with Synopsys implementation solution
• Architecture exploration and early software development with virtual/physical prototyping
• Formal verification of datapath designs
• Using emulation for AI software stack validation
• AI-enabled productivity and performance innovation
• Using virtual test environments for network system validation
• Using AI-ready IP to meet processing, memory, and connectivity requirements for deep learning applications

Aerospace & Defense

• Optimizing FPGA design for best area and performance
• High reliability design, debug and verification
• DO-254 compliance and methodologies
• Electrical system design validation
• Trust and hardware security verification

Automotive

• Accelerate automotive software development and validation with virtual prototyping
• Complete functional safety verification with industry-leading fault simulation, formal and static verification
• High reliability design techniques for automotive designs
• Hardware security verification
• Implementing safety critical designs for automotive applications
• Designing ISO 26262 required In-System Test using Synopsys tools
• Accelerating ISO 26262 certification with ASIL Ready Certified IP

Analog/Mixed-Signal Verification

• Application of Monte Carlo analysis to improve AMS circuit robustness with HSPICE, FineSim or CustomSim
• How to minimize design margin with accurate reliability analyses including heat-aware EM, IR and device aging with CustomSim, FineSim or HSPICE
• Best practices in mixed-signal verification with advanced digital verification methodology with CustomSim and VCS
• How to verify power and signal integrity for multi-gigabit circuits with HSPICE
• Application of CustomSim Circuit Check to find electrical rule violations in circuits

Custom Implementation

• Productivity gain from using Custom Compiler Template Assistants (Symbolic Editor)
• Productivity gain from using Custom Compiler In-Design Assistants (DRD, EM/IR, RCx)
• Productivity gain from using Custom Compiler’s Co-Design with IC Compiler II
• Robust analog design from using Custom Compiler and SAE (Simulation Analysis Environment) 

Design PPA, TTR Optimization and Signoff

• Optimal design flow for digital implementation of advanced  node designs
• Accelerating turnaround time for large designs with Design Compiler Graphical and IC Compiler II
• How to achieve best Performance, Power and Area for Arm CPUs
• Using parallel processing to accelerate physical and full chip timing signoff
• Accelerating full chip TAT for large designs using IC Validator physical signoff
• Optimization techniques for low-power IoT designs
• Early time-based peak power analysis with PrimePower with RTL-based vectors
• Using physical-aware ECO capabilities to improve PPA and accelerate timing closure

Silicon Test and Yield Analysis

• Success with early RTL analysis, physically-aware and area-saving DFT, higher defect detection, lower pattern count/test time, faster and volume diagnostics
• Highlighted applications include automotive, mobile, and processors

Verification Efficiency

• Cloud-based verification
• Faster and better convergence using formal methods
• Verification coverage planning and closure
• Best practices for static verification (Lint/CDC/RDC/SDC/LP) signoff
• Accelerating verification and debug for advanced protocols
• Innovations in verification methodology for optimized performance

Hardware-based Verification

• Power analysis for edge and data center SoCs
• Advanced emulation-based debugging
• Validation of system performance on a SoC or subsystem
• Accelerating software bring-up with emulation and prototyping
• 5G system validation through emulation and prototyping
  

Successful IP Integration into SoCs

• Interface IP such as PCI Express, DDR, USB, MIPI, 56G/112G Ethernet, etc.
• Embedded ARC processors & embedded vision processors
• OTP non-volatile memory, memory compilers & logic libraries
• SoC/IP integration for automotive, AI and cloud computing designs