SNUG Silicon Valley 2019 Proceedings

Finite State Machine (FSM) Design & Synthesis using SystemVerilog

Clifford Cummings - Sunburst Design; Heath Chambers - HMC Design Verification

StarRC Parameterized Spice Capability

Jagannathan Vasudevan, Cole Zemke, David Permana, Sharon Jo, Srilata Raman - GLOBALFOUNDRIES

Accelerating Debug of Assertions by Leveraging Synopsys HAPS Prototyping with Verdi

Marek Sulocha, Sriram Manjunath - NVIDIA

Using Machine Learning for Characterization of NoC Components

Benny Winefeld - ArterisIP

Improving Characterization Turnaround Time: Production Library Characterization in 24hrs

Laker to Custom Compiler: A Journey

Sarvesh Ganesan - Microsoft