Verification Methodology Manual for SystemVerilog

Author Bios

Janick Bergeron is a Fellow in the Verification Group at Synopsys, Inc. He is the author of the best-selling book Writing Testbenches: Functional Verification of HDL Models and the moderator of the Verification Guild. He holds a Masters degree in Electrical Engineering from the University of Waterloo, a Bachelor of Engineering from the Université du Québec à Chicoutimi, and a MBA degree from the University of Oregon.

Eduard Cerny, Ph.D. (McGill University), is a Scientist in the Verification Group at Synopsys, Inc. He joined Synopsys in 2001 after 25 years in academia, as Professor of Computer Science at the Université de Montréal. His interests have been in design, verification and test of hardware, and he is author of many articles in these areas.

Alan Hunter, BEng(Hons), MSc, is a Verification Architect at Arm Ltd and leads the design verification methodology work for Arm worldwide. This work covers all areas from CPU design verification through systems and system component design verification. His main areas of interest include optimizing design verification efficiency and quality, formal methods, and determinism in the design verification flow.

Andrew Nightingale, BEng(Hons), MBCS CITP, is Vice President, System IP Marketing at Arm Ltd. Previously he was a consultant engineer at Arm and led the SoC Verification group in Arm’s Cambridge and Sheffield design centers for several years. The Arm® System IP portfolio includes interconnects, security IP, system controllers, debug and trace IP built upon the open Arm AMBA® standard.