ARC Processor Virtual Summit

10:00 a.m. – 10:40 a.m. PT

SoC Level Safety Management, A Software View

Speaker: Anatoly Savchenkov, Software Engineering Manager, Synopsys

Increasing complexity of automotive ICs consisting of multiple heterogeneous processors and accelerators, I/O interfaces and custom hardware blocks raises unprecedented challenges for safety architects. Safety management tasks including safe boot, periodic safety testing and handling of runtime safety escalations traditionally are done in hardware making them expensive and not easily reusable in multiple designs. This presentation describes how Synopsys safety hardware architectures are enabled by ARC embedded safety software to deliver increased usability, extensibility, and robustness for SoC level safety management tasks.

10:40 a.m. – 11:20 a.m. PT

Implement ASIL D-Compliant ARC Processor IP Using Synopsys’ Native Automotive Design Solution

Speaker: Shiv Chonnad, Sr. Staff Functional Safety Engineer, Synopsys

Next-generation autonomous driving and advanced driver-assistance systems (ADAS) applications require complex safety-critical electronic components. The SoC designs used in these electronics should adhere to the ISO 26262 functional safety (FuSa) standard to achieve the highest automotive safety integrity level (ASIL). Synopsys offers the broadest portfolio of silicon-proven automotive-grade IP, which is ISO 26262 certified up to ASIL D, for use when developing safety-critical SoCs. Synopsys’ new native automotive RTL-to-GDSII solution, driven by FuSa intent, enables designers to efficiently implement and verify FuSa mechanisms in order to achieve target ASIL with improved quality-of-results and ease-of-use. The Solutions Group IP team has successfully leveraged the native automotive RTL-to-GDSII solution. This presentation will describe the ASIL D-compliant ARC processor IP and the new native RTL-to-GDSII solution, the resulting implementation flow with an ARC HS46 dual-core lock-step (DCLS) processor, and benefits for the SoC designer.

11:20 a.m. – 12:00 p.m. PT

Addressing the Challenges of RADAR, LiDAR & Vision Sensor Fusion for Next-Generation Automotive ADAS Systems

Speaker: Pieter van der Wolf, Principal R&D Engineer, Synopsys

Automotive ADAS systems use multiple sensing technologies, RADAR, LiDAR and Imaging to create a 360 degree view of surroundings. Each different sensing technology has its own advantages to environmental conditions. Complexity is increasing in ADAS systems, while demanding a reduction in component cost. This presentation will go through the computation capabilities of various Synopsys ARC processors as well as discuss the use of cross computation and sensor fusion functionality to improve the quality of sensor detected object data in automotive ADAS systems.

10:00 a.m. – 10:40 a.m. PT

Solving the Challenges of the Evolution Drive from Bluetooth LC3 to LC3Plus Codecs

Speakers: Michael Rougeux, Director of Software Engineering, T2 Labs, and Graham Wilson, Sr. Product Marketing Manager, Synopsys

In January of 2020, the Bluetooth SIG announced that the Bluetooth LE Audio standard will include the Low Complexity Communications Codec (LC3), with several companies announcing available solutions for the Bluetooth LC3. The Bluetooth LE Audio standard with LC3 is expected to gain large amounts of traction in the industry, enabling the next-generation of Bluetooth audio solutions. Technology leaders in the industry are also looking at the next evolution step of the Bluetooth LC3 with the LC3 Plus codec specification. LC3Plus comprises all features of the Bluetooth LC3 plus an advanced PLC for transmission robustness, lower delay modes down to 5ms at a 2.5ms packet size, and higher resolution audio modes. LC3Plus enables a new range of applications as well as technical challenges. This joint presentation between T2 Labs and Synopsys details the new target applications of LC3 and LC3Plus and the technical challenges for proposed solutions of LC3 and LC3Plus codecs.

10:40 a.m. – 11:20 a.m. PT

Trends in Machine Learning for Edge Applications

Speaker: Pierre Paulin, Director of R&D, Embedded Vision, Synopsys

Embedding computer vision and deep learning at the edge remains challenging today because of 1) huge computational and memory requirements, and 2) the accelerating pace of innovation for algorithms that perform modern vision and sensing tasks. CNN graphs particularly are rapidly evolving to improve the accuracy and speed of learning and inference. Mapping vision and deep learning algorithms to low-power embedded platforms is challenging because they are often very demanding on compute, bandwidth, and accuracy.

In this presentation, we will discuss the latest trends in machine learning for edge applications, including emerging models like EfficientNet and new techniques like Transformers. We will review the key challenges and opportunities for embedded implementation with a focus on new techniques for bandwidth optimization. This presentation will also explain how the latest trends are shaping enhancements to the DesignWare EV Embedded Vision Processor IP family.

11:20 a.m. – 12:00 p.m. PT

A Brief History of Time – of a Bluetooth Controller

Speaker: David Peavey, System Engineer, Intel

The Bluetooth Core Specification has undergone several rapid changes over the past two decades.  The addition of Bluetooth low energy in 2010 further accelerated the evolution of the technology. Bluetooth is widely used today in PCs, mobile phones, headsets, wearables, and a myriad of IoT devices.  As expected with any immensely successful technology in an increasingly competitive landscape, the bar is being raised on performance and low power consumption requirements for each successive product generation. The Bluetooth controller – considered the “brains” of the Bluetooth system – has constantly adapted and kept up with the requirements.  This paper traces how the growth of the Bluetooth specification, use cases, and Key Performance Indicators (KPIs) evolved the controller hardware architecture over the years.  Despite the ever-increasing performance and use case demands, the march towards lower and lower power consumption is relentless.

10:00 a.m. – 10:40 a.m. PT

The Future of High-Performance Embedded Processing:  How You Get from Here to There

Speaker: Paul Stravers, Principal R&D Engineer, Synopsys

The requirements for embedded applications are changing as high-performance infrastructure spreads from the cloud to the edge and end points of the internet.  High-end performance requirements are rapidly increasing but there are limits on power and area in embedded applications that must be accounted for.  This is restricting what can be done to increase processor performance and is driving the use of configurable multicore solutions and specialized hardware accelerators.  This presentation will look at the future structure of embedded processors that deliver the performance, scalability and flexibility needed to address the ever-increasing performance requirements for storage, automotive, networking, mobile and other high-end embedded applications.

10:40 a.m. – 11:20 a.m. PT

What’s New In Zephyr For ARC Processors

Speaker: Alexey Brodkin, Software Engineering Manager, Synopsys

"The Zephyr Project strives to deliver the best-in-class RTOS for connected resource-constrained devices, built to be secure and safe" is the project's vision statement. And this is being achieved with continuous improvements made by the huge community of developers from different companies and locations around the globe. These improvements are not just fixes for particular platforms or use-cases, but they also include a well-planned development of higher-level substances such as an approach to safety certification, as well as  build & test infrastructure enhancements. During this presentation we will discuss the most important and interesting changes that were made in the Zephyr project last year and we will look at how mutual efforts between Synopsys engineering and the Zephyr community can help designers of ARC processor-based systems build complex and secure products based on Zephyr RTOS.

11:20 a.m. – 12:00 p.m. PT

High Bandwidth Data Protection Case Study for the Supercomputing Era

Speakers: Andrew Elias, Sr. Security Architect, Synopsys & Craig Forward, Senior Security Products Development Lead, Synopsys

Cloud computing is going through a significant overhaul and continues to grow globally with increasing presence of hyperscale cloud providers for big data and analytics. In-house data centers are increasingly going off premises, resulting in the co-location of data centers that manage and store data for companies and application developers to improve scalability and reduce IT costs. This huge, and growing, amount of data with confidential and critical information must be protected. New laws and regulations to comply with data privacy rules put additional pressure on solution providers to secure their systems and data.

This presentation will highlight a complete, high-grade security use case that addresses the performance and latency needs for supercomputing applications starting with the SoC. Attendees will learn how to protect data at high speed based on AES-GCM encryption while managing the keys and other security services with a hardware secure module with root of trust.