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Selecting NVM IP for PMICs: 4 Key Considerations
Krishna Balachandran, Product Marketing Manager Sr. Staff, Synopsys
Introduction
Power Management Integrated Circuits (PMICs) are the first to turn on and the last to turn off in a system. They perform the task of delivering the right voltage to component chips by regulating or boosting the voltage levels.
Analog rich PMICs are especially susceptible to semiconductor manufacturing variations. Calibration is the post-manufacturing step involving determination of these variations vs. expected values and cancelling or compensating for these variations.
Today’s smart PMICs include programmable power up and power down sequences, external event detection, system monitoring for over voltage and current conditions that can cause damage to the PMIC, fault handling wherein the PMIC takes control of the system and prevents power failure, and algorithmic implementations of battery capacity prediction and battery management, all of which are implemented in digital logic. Depending on the end application, some or all these functions need to be activated. Configuration allows building a platform PMIC for a range of applications and enables customization of the functions.
PMICs can be calibrated and configured with Non-volatile memory (NVM) to deliver the right voltage and power sequence for the target application or provide configurable functionality for the end system.
Some PMICs are calibrated and configured once at the factory, and for these, and an area-efficient One-Time Programmable (OTP) NVM is the best choice. When a PMIC is expected to be calibrated and re-configured multiple times during its lifetime, a Multi-Time Programmable (MTP) NVM can be used.
BCD silicon processes combine the strengths of three different process technologies onto a single chip: Bipolar for precise analog functions, CMOS for digital design, and DMOS for power and high-voltage elements. This combination of technologies brings many advantages to PMICs: Improved reliability, reduced electromagnetic interference, and smaller chip area. Because of these advantages, most PMIC makers have chosen a BCD process to manufacture PMICs.
PMICs can be manufactured in multiple ways. They are cost-sensitive, so PMIC makers generally choose manufacturing processes with a minimum number of mask layers. To help the PMIC makers, NVM IP vendors must align with the PMIC makers and offer the IP in multiple variants of the same process. NVM is very sensitive to manufacturing processes and must be silicon qualified for the combination of devices used by the PMIC maker.
Figure 1: Antifuse-based OTP is inherently secure—it’s impossible to tell if this OTP has been programmed
Role of Embedded NVM in PMICs
PMICs are widely used in mobile applications including smartphones, wearables, hearables, laptops, and tablets. They are also used in smart motor control, lighting control, and industrial control applications.
Today’s PMICs are smart and configurable and are built in a modular fashion. Depending on the end application and the voltages or power sequencing required, configurable firmware stored in an NVM customizes the PMIC for a particular application. When frequent firmware updates are required as in automotive applications, re-programmable NVM or MTP NVM is the best choice. However, if firmware is expected to be programmed only once during the lifetime of the product, a more area-efficient IP, in the form of an OTP NVM, is preferred.
Additionally, the NVM is used to store values of output voltages, current limits, power-on-reset delays, power-up delays, ramp rates for voltages, standby mode settings, and power good and invalid power condition settings.
Since a PMIC has analog circuitry, trimming and calibration are required after manufacturing either in the factory or in the field to get the product ready for its intended use. These settings are also stored in the embedded NVM.
Why Not Use Foundry-Sponsored Electrical Fuses?
Designs in mature process nodes like 350nm and 250nm were simple power management ICs. They were typically mostly analog with little to no digital control logic. Foundry-provided electrical fuses were used to store calibration information for the analog circuitry (up to 2Kb). At small capacities and at mature process nodes, foundry-provided electrical fuses were area efficient, reliable, and served their purpose. As PMICs became smarter, and more digital control was introduced, and as they migrated to more advanced process geometries, much larger memory capacities are needed.
Electrical fuses are not area-efficient at larger capacities and suffer from re-growth issues over the life of the product, making them unreliable. Electrical fuse re-growth stems from electromigration that causes the blown fuses to re-attach and change the values stored over time. In addition, electrical fuses can’t be practically used to store firmware, which require 64 – 256Kb of capacity. Finally, electrical fuses do not provide any security, rendering the information stored in them to be visible under a Scanning Electron Microscope and making them vulnerable to hacking attempts.
NVM for Advanced Nodes
MTP and antifuse OTP NVM, which went into widespread commercial production about 10 years ago, are fundamentally reliable and scalable. No special masks or process steps are required to manufacture the NVM device. They have entered volume production at 180nm and at smaller geometries in BCD processes. As BCD processes have scaled down, MTP and antifuse OTP have been designed in advanced nodes up to 55nm.
NVM Reliability
In harsh environments for automotive and industrial applications, reliability is another key requirement. When properly qualified at high operating temperatures of up to 150°C and even 175°C, and tested for early life failure rates, MTP and antifuse OTP NVM have demonstrated excellent reliability, endurance, and data retention over the lifetime of the product.
NVM Security
Antifuse OTP NVM is not easily susceptible to any passive or invasive security attacks attempted by altering the voltage or temperature. Since antifuse OTP NVM operates on the principle of oxide breakdown to represent a programmed bit, it is impossible to visually distinguish between a programmed and an unprogrammed bit even with the aid of a scanning electron microscope.
MTP and antifuse OTP NVM that are specially designed for PMIC applications deliver on all fronts: they are cost-effective, consume minimal power, optimize programming and erase cycle times, and provide fast read times at system boot.
Considerations for Choosing NVM for a PMIC
When selecting the foundry for manufacturing, a PMIC designer starts with the following considerations:
- End market (consumer or automotive)
- Product requirements for the end market
- Choice of the process node (based on previous analysis)
- Projected manufacturing volumes
- Anticipated wafers needed in a certain time frame
- Foundry’s ability and willingness to
- allocate the wafers for the PMIC maker’s project
- meet the expected wafer price.
Once these decisions are made, the PMIC maker begins looking for NVM IP that is available and qualified in the foundry and process node of choice.
The 4 most important considerations for selecting the NVM IP are:
- Availability
With the recent global wafer demand spiking for PMICs and capacity running tight at the foundries, PMIC design houses are scrambling to find a semiconductor manufacturing vendor that can provide the wafer allocation at a reasonable price and in time to meet product ramp-up forecasts.
- Total cost of ownership
The total cost of ownership is the sum of the cost of acquisition of the IP, the silicon-cost, and the cost of programming the NVM.
- Security
NVM that stores critical voltage and current values, and power sequences, and potentially firmware code must be secure to ensure the security of the system.
- Reliability and endurance
NVM targeting automotive applications must be designed and verified against the automotive Physical Design Kit (PDK) when available from the foundry, and following strict automotive design guidelines.
DesignWare NVM IP for PMIC Applications
DesignWare® MTP NVM IP and DesignWare OTP NVM IP offer scalable and reliable embedded memory NVM solutions in standard CMOS and BCD processes without requiring additional process or mask steps. The patented technologies offer small silicon footprints and optimize programming and read access times. Built-in security features in the antifuse OTP NVM protect against active and passive attacks, tampering, hacking, and reverse engineering.
The customizable macros allow design flexibility for PMIC applications that require storage of trimming, calibration, and configuration information in a secure fashion.
Qualified for automotive AEC-Q100 grade 0 and 1 temperatures, the DesignWare MTP NVM IP and DesignWare NVM OTP NVM IP accelerate SoC-level development even for harsh automotive environments. They are available across multiple foundries and process nodes.
Synopsys’ MTP and antifuse OTP NVM IP have been adopted in a broad range of systems including the most advanced PMICs in consumer and automotive applications.
Conclusion
All systems need carefully delivered voltages and currents to components for reliable and predictable functioning. PMICs deliver carefully controlled voltages and currents for proper functioning of consumer, automotive, and industrial applications. PMICs are analog rich designs that need calibration to compensate and correct for semiconductor manufacturing variations. Newer PMICs incorporate increasing amounts of digital logic allowing customization and configuration targeted for multiple end applications. OTP or MTP NVM is the ideal choice to store calibration and configuration information.
Synopsys DesignWare NVM IP provides OTP and MTP NVM in standard CMOS and BCD process technologies with no additional masks or processing steps. Synopsys’ MTP and antifuse OTP NVM IP offers small silicon footprint, and its built-in security features protect against active and passive attacks, tampering, hacking, and reverse engineering. They have been adopted in a large range of systems covering the highly developed PMICs in consumer and automotive applications.
For more information, download the white paper: Calibrate and Configure your Power Management IC with NVM IP