Why Attend?

RISC-V International is a large member organization building the first open, collaborative community of software and hardware innovators changing the processor landscape. The global RISC-V community – including technical, industry, domain, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara, California to share technology breakthroughs, industry milestones, and case studies.  

Synopsys is honored to take part in the RISC-V North America Summit this Fall. Synopsys, a premier partner in this rich ecosystem, is enabling successful RISC-V designs with comprehensive, ready-to-use design exploration, verification, software development, and IP solutions that enable designers to harness the full potential of RISC-V.     

Join us to find out what’s new with RISC-V for automotive, data centers, wearables, AI/ML, security, software and more!

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Synopsys Exhibit Booth G2

Tuesday, October 22, 2024
10:45 a.m. - 7:00 p.m.

Wednesday, October 23, 2024
10:45 a.m. - 4:00 p.m.

 

Synopsys Presence

Tuesday, October 22, 2024

10:15 - 10:25 AM PDT
Keynote: Shaping the Future of Automotive Computing with RISC-V
  • Rich Collins, Executive Director, ARC-V Product Management, Synopsys
01:05 - 01:15 PM PDT
Demo: More Than Point Tools: RISC-V Solutions
  • Larry Lapides, Sr. Director, Product Management, Synopsys
02:55 - 03:13 PM PDT
Combined Dynamic and Formal Verification Approach to Processor Verification
  • Aimee Sutton, Sr. Director, Product Management, Synopsys
  • Xiaolin Chen, Sr. Director, Applications Engineering, Synopsys
03:35 - 04:15 PM PDT
ISA & Design Tools Poster Session: RISC-V "V" Vector Extension (RVV) with Reduced Number of Vector Registers
  • Eino Jacobs & Dmitry Utyanski, Synopsys

Wednesday, October 23, 2024

02:15 - 02:33 PM PDT
Software Simulation Is the Key to Success for Customized CPUs and Complex SoCs
  • Jon Taylor, Senior Director, Product Management, Synopsys
03:15 - 03:55 PM PDT
AI/ML Poster Session: Creating Custom RISC-V Processors Using ASIP Design Tools: A Neural Network Acceleration Case Study
  • Gert Goossens, Executive Director, R&D Engineering, Synopsys


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