NAND Flash Scaling and TCAD Application

NAND flash memory has numerous applications, from mobile phones to data centers.  It also has been widely adopted in Solid State Drives (SSD) over the last 10 years.  NAND scaling has continued rapidly into the current 3D NAND era where not only are the number of layers growing rapidly, from 32L in 2017 to 300L in 2024, but also the memory is compacting in other dimensions.  Currently NAND capacity in a single SSD drive can be as high as 128TB and will soon be increasing to 1PB.

There are challenges faced due to the continued aggressive physical scaling in the 3D NAND era. Capital expense (CapEx) has increased dramatically from one generation to the next due to the complexity of stacking 3D cells vertically. The growth in the total amount of capacity from 3D NAND products has flooded the markets with a lot of bits, and therefore has driven down the price of flash products. This benefited many applications but caused difficulties for NAND manufacturers. The new 8th generation chips from WDC are a new generation providing improved technology with good cost reduction and high performance by using CMOS Bonded Array (CBA) technology.  The application of TCAD tools in 3D process technology helped WDC design these complicated structures efficiently and economically.

Accelerating Circuit Simulation using GPU

This presentation explores the utilization of GPU acceleration to enhance the speed and efficiency of fast spice circuit simulation. Traditional CPU based circuit simulation encounter computational bottle necks particularly on large custom memories with PDN (Power Delivery Network) and hindering design iterations. Timing needs to be very accurate at lower geometry nodes with PDN and any inaccuracy can result in silicon bugs. To circumvent silicon bugs, excessive padded margins are adopted, resulting in a compromised performance. PrimeSim simulator from Synopsys with GPU computing support enable the accurate timing analysis with PDN from 19days to 4days (5x improvement). This presentation aims to bring out various details and facets of GPU based sims in a qualitative and quantitative means.

High Verification Coverage with ESP in Full custom SRAM Memory Design

Over 50 percent of the total silicon real estate in today’s SoC is consumed by memories. And as designs move toward sub-nanometer process technology, functionalities such as redundancy, ECC, BIST, pipelining, etc. are being added to these designs, resulting in significantly higher functional complexity.

ESP is an equivalence checking tool commonly used for functional verification of custom designs such as embedded memories, standard cells , Io’s etc. It compares transistor-level SPICE netlist with the reference Verilog. It is used to cover various possible combinations of cases to test memory functionality & could also ensure first level of design sanctity.  E.g. ESP uses formal techniques to quickly verify that the redundancy logic added to the memory array to replace defective cells and improve yields is performing correctly. In this presentation we will be sharing functional verification of SRAM memory in various modes. Also, ways to debug the errors & generate waveform when failure doesn’t exist.

Hyperconvergence of Static-Aware Synthesis Solution for Samsung Memory

This presentation will introduce CDC verification and power saving related technologies from RTL to netlist. CDC verification is performed in RTL generally, sign-off for CDC is performed through VC Spyglass. Once CDC verification of RTL, need to check for CDC problems that may occur due to the converted netlist. Typically, CDC analysis is difficult to manage at netlist. We can automate CDC verification by applying the RTL CDC verification results to the netlist through hyperconvergence. In addition, Power can be saved through the "Unexpected Self Clock-Gate Control" technology of hyperconvergence.

The Path to Emerging NVMs goes through Co-Simulation with Synopsys

Performance demands of emerging applications are driving the industry to look for new memory technologies and architectures. In this talk we will introduce Weebit ReRAM, an emerging non-volatile memory (NVM) technology with unique advantages for SoC designs across applications from IoT and MCUs to edge AI and automotive to future neuromorphic computing use cases. With ReRAM, a combination of precision analog and smart algorithms is key to achieving high performance. This presents unique verification requirements that make co-simulation a must-have tool before tapeout. We will discuss how using Synopsys verification tools for co-simulation can lead to a significantly higher level of confidence than traditional methods.