Synopsys Cloud
Cloud native EDA tools & pre-optimized hardware platforms
Request a Free Trial →
Join us at the upcoming workshop to learn about the latest features and flows to address signoff Physical Verification challenges for advanced digital SoC designs and complex custom designs using Synopsys’ ICV solution.
In this workshop, we will discuss key methods to improve design convergence, demonstrate newer technologies to improve TAT, QoR and provide opportunity to hear success stories from leading semiconductor companies
Key takeaways:
- New learnings about Physical Verification, Advanced features for Efficient handling of full chip scale complexities, Native Integration to Fusion Compiler Environment
- Showcase live demos on these tools by Synopsys/customer experts.
- Customer testimonials on usage and benefits of ICV.
Agenda:
9:00 – 9:30 a.m: Welcome and Coffee
9:30 – 13:30 p.m: Physical verification – ICV
13:30 – 14:00 p.m: Lunch
14:00 – 14:30 p.m: Intel to present Efficient Layout Integration Methodologies for complex Full Chip Convergence