What is Low Power Design?

Companies are continuing to push the boundaries on new features and functionality, all packed into portable, handheld, and battery powered devices. For such products, improving the battery life by minimizing power consumption is a huge differentiator and extremely important to their end users’ applications. Improving the time it takes for a device to go from OFF/SLEEP state to ON/ACTIVE state is just as important, as the end user wants to have a seamless experience along with longer battery life.

For “plug-in” products, power consumption is also important because it can affect the overall cost of systems by requiring heat sinks and elaborate cooling systems, increasing electricity costs, etc. For example, in server farms, where massively parallel systems are used, a reduction in power for a single chip can result in significant power savings because it is used throughout the system. The power and cost savings by upgrading these systems with newer and more power efficient ICs can be significant.

Assuming an example where the system has been specified, system simulations have been performed, microarchitecture is completed, low power choices for technology node, IP, etc., have been made, and coding of RTL and UPF are done. Given this, there are five main phases for low power design and verification methodology to be used to design the IC.

Static Power Verification and Exploration

In static verification, the first step is to ensure the inputs to the design flow (RTL, UPF, and SDC) are structurally and syntactically correct. By definition, static verification doesn’t use test vectors, so this is a very efficient way to review inputs before going into simulation or implementation flows. Lint and CDC checks are important in general to ensure your RTL is clean. UPF checks can be done either independently or with the corresponding RTL to ensure they are clean and SDC can also be statically checked along with RTL as well. In power exploration, early estimates for power for the RTL can be driven, either with estimated switching or actual waveforms from simulation. Choices can be made early on to improve the overall architecture of the design by performing early RTL power analysis.

Dynamic Power Verification and Analysis

In dynamic power verification, there are several important aspects to check. First off, does the sequence for the PMU control signals work correctly to shut down, clamp for isolation, save, restore, remove isolation clamp, and power up. This is an extremely important check with the design RTL and UPF together to make sure the design is functioning properly. Next, what type of waveforms and toggle activity are seen in the design? This will determine the dynamic power used since it depends on activity factor. The higher the activity factor, the more power is being used. Hence, the waveforms produced are very important to accurately estimate power both early and late in the process.

Software Driven Power Analysis

For emulation-based low power flows, it’s important to be able to capture the right peak windows for the design’s power profile. Emulation allows review of a much wider set of data, enabling one to choose
the windows that would be most valuable to generate waveforms to estimate power.

Power Implementation

RTL-based predictive power estimation, logical synthesis, DFT insertion and physical implementation all have important low power specific roles to play. RTL-based predictive power estimation allows, very early on, to make RTL modifications with early power estimates. In logic synthesis, the RTL, SDC, and UPF, now fully verified both statically and dynamically, are mapped to technology gates. Power-specific isolation, level shifter, and retention cells are mapped to gates as well, where timing, area and power are all part of the cost function for generating a Netlist and associated UPF’. DFT insertion occurs as well, often simultaneously during this time. Once the Netlist and UPF’ are complete, another round of checks is done statically and dynamically at this level – once clean, the results are input to physical Implementation. In physical implementation, floorplanning is done with macro placement and power routing in mind. Then placement is performed where power switches are physically inserted and placed; and iterations of placement, routing estimation, logical optimizations, and clock tree synthesis are performed to once again trade off for timing, area, and power. Finally, the routing step occurs, where pre-route of the priority signals (clock, power enables, switch connections) is done followed by detailed routing of the rest of the design – all with emphasis on reducing power more granularly, while still trying to meet the timing and area targets.

Signoff

UPF consistency should once again be checked during signoff. However, this time with the Netlist and UPF’ from logic synthesis and PGNetlist and UPF” from physical implementation. This will ensure that the connections and changes made to the netlist and UPF are consistent and clean, and the power intent is preserved. Logical equivalence checks comparing RTL and UPF vs. Gates and UPF’ vs. PGNetlist and UPF” ensures the logical functionality is preserved. Finally, static timing analysis should be performed with UPF to ensure the design meets timing; and power analysis with detailed waveform behaviors to give accurate power estimation results.

The low power design tools needed for each phase of the methodology are:

1. Static Power Verification and Exploration. Static verification requires tools for Lint and CDC, to ensure the RTL is clean.  For UPF, a UPF checker is necessary to ensure the UPF is clean.  For power exploration, a RTL power estimation tool is required.
2. Dynamic Power Verification and Analysis. A power-aware simulator is necessary to validate the power sequence and generate waveforms. A power-aware debug tool is also necessary, along with tools that can leverage RTL simulation data and translate to Gate level simulation data, as this is vital for saving time and providing very accurate waveforms for power analysis.
3. Software Driven Power Analysis. With emulation, cycle-based power can be generated, observation of much longer behaviors, and the right power/timing windows for power analysis can be chosen.
   
4. Power Implementation. RTL-based predictive power estimation, logic synthesis, DFT insertion (Scan Insertion, MBIST, Logic BIST, etc.) and physical implementation (Floor planning, Placement, Clock Tree Synthesis, Routing) are necessary to implement the low power design.
   
5. Signoff. UPF checking for Netlist and UPF’ and PGNetlist and UPF” is critical to ensure the power intent is correct and preserved through the flow. Logical equivalence checking with power-aware capability is also critical to ensure logical functionality is preserved through the flow. Static timing analysis and power analysis tools are critical to verify timing and give accurate power estimation results.