George Kokai, Sr. Circuit Design Methodology Engineer

“To elaborate on my experience using PrimeSim, I saw long simulations be reduced from run times of days or weeks down to hours or days. That kind of run time reduction can open up the door on the amount of pre-tapeout verification that can be achieved. Giving greater coverage and confidence of the first tapeout going to production.”  

Synopsys customers can watch the complete video. 

Chuan Lyu, Digital IC Design Engineer

“The proposed flow suits the new design structure by supporting the analog submodule replacement with SPICE. It provides more flexibilities for different test cases and provides more tool options. It also clearly defines the files that need to be maintained for Digital and Analog Engineers. And also, this one is backward compatible for the conventional design.” 

Synopsys customers can watch the complete video.

Jean-Christophe Lafont, Memory Design Expert

“With this feature, the runtime went down to 14 hour, in addition, we added better accuracy.  In conclusion, the improvements we have made meet the goal we have set at the beginning of this work… There was a total performance gain of 12x, in terms of runtime.” 

Synopsys customers can watch the complete video.