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SNUG 2018 IC Validator Lunch Panel
Extreme Physical Verification Productivity Gains with IC Validator
The IC Validator panel at SNUG Silicon Valley focused on how leading companies address the challenges, technologies and solutions related to a convergent and efficient physical signoff flow that enables the fastest path to production silicon.
With increasing manufacturing complexity at advanced technology nodes and shrinking design schedules, physical verification turnaround time is critical to deliver tape-outs on schedule.
On March 22 2018, Synopsys hosted an IC Validator panel at SNUG in Santa Clara, CA. At this event, foundry and market leading technologists discussed the verification challenges designers face today, and the technology required for a convergent and efficient physical signoff flow delivering the fastest path to production silicon.
Guest Speakers:
Event Emcee
Elango Velayutham
Senior Manager, Applications Engineering, Synopsys
Silicon Valley IC Validator SNUG Panel
James Chen
Senior Director, Advanced Technology Group, NVIDIA
Accelerating Physical Verification Productivity Using IC Validator
Henry Selvaraj
Principal Engineer, Juniper Networks
Physical Verification at Socionext
Hiroaki Hanamitsu
Senior CAD Engineer, Socionext
IC Validator: Exploring Tailoring with Power Threads
Henry Bonges
Layout Automation Consultant, IBM