Go Back
By Industry
By Technology
Mastering AI Chip Complexity
Mastering AI Chip Complexity

Explore challenges and solutions in AI chip development

Download eBook
Multi-Die Innovate Faster eBook
Innovate Faster with Synopsys Multi-Die Solution

Accelerating success from early architecture to manufacturing.

Download eBook
View All Solutions
Explore Silicon Design, Verification & Manufacturing

Synopsys is a leading provider of electronic design automation solutions and services.

Families
Optical Design
Photonic Design
Design
3D Image Processing
Verification
Modeling & Simulation
Manufacturing
Try Synopsys Cloud
Synopsys Cloud

Unlimited access to EDA software licenses on-demand

Request a Free Trial
Explore Silicon IP

Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs.

Interface IP
Processor IP
Foundation IP
SoC Architecture
Security IP
SoC Infrastructure IP
IP Accelerated
IP Markets
Synopsys IP Portfolio Cover
Synopsys IP Portfolio
Download Brochure
Synopsys IP Technical Bulletin
Read Latest Issue
Explore Systems Verification and Validation

Synopsys is a leading provider of hardware-assisted verification and virtualization solutions.

Emulation & Prototyping
Verification IP
FPGA Development
System Test Generation
Virtual Prototyping
View All Products
Company Overview
Resources
Synopsys and Ansys are Now United
Synopsys and Ansys are Now United
Learn More
Synopsys Blog
Synopsys Blog

Insights that shape the future.

Visit Our Blog

Accelerate Custom Layout using Custom Compiler’s User-Defined Device (UDD) – Part 2

Current Time 0:00
Duration 0:00
Loaded: 0%
Stream Type LIVE
Remaining Time 0:00
 
1x
    • Chapters
    • descriptions off, selected
    • captions off, selected

        In part 2 of this video series, Shabbir Batterywala, Synopsys Scientist, shows how layout designers create complex parameterized custom layout structures in an easy-to-use graphical environment, without any programming.

        See more video whitepapers