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Synopsys IP Videos
ARC VPX DSPs - Scalable Vector Processing for Advanced Sensor Fusion
Learn how the highly configurable and scalable Synopsys ARC VPX Processor IP is revolutionizing sensor fusion applications with its advanced pre-processing and AI decision-making capabilities, customizable for Radar, vision processing, and AI offload engines.
Lauterbach TRACE32 Development Tool on Synopsys ARC-V RISC-V Processor IP
Learn how designers can benefit from the combination of Lauterbach TRACE32® Development Tools for RISC-V and Synopsys ARC-V™ IP. This effective duo enables designers to more easily analyze, optimize, and certify their power-efficient, ARC-V-based SoCs for embedded applications.
Synopsys & TASKING RISC-V Solutions for Safety & Security Critical Automotive Applications
Learn how designers benefit from the combination of TASKING's VX-Toolset for RISC-V and Synopsys ARC-V™ IP, by gaining access to tools to develop safe, secure, and power-efficient SoCs for safety-critical applications. Discover how TASKING and Synopsys collaborate with automotive customers to create a trusted ecosystem that meets ISO 26262 and ISO 21434 standards.
ARC VPX DSPs - Scalable Vector Processing for High-Performance Embedded Applications
Learn how Synopsys ARC VPX DSPs’ versatile yet configurable architecture efficiently addresses compute-intensive signal processing and AI workloads, from automotive to vision and natural language processing and any kind of sensor fusion.
224G and 112G Ethernet PHY IP enable 800Gbps and beyond at DesignCon 2024
Watch a variety of Ethernet IP demos at DesignCon 2024, including the world's first 224G asynchronous true-long reach demo equalizing 40+dB of insertion loss! You can also see 224G, 112G and 800G Ethernet interop demos showing robust performance.
Synopsys’ Silicon-Proven USB 3.2 Device IP Operating at 20 Gbps
This video features Synopsys silicon-proven USB 3.2 Device IP, implemented in FPGA, operate at 20Gbps with three different hosts.
World’s First PCIe 6.0 Interop with Intel’s PCIe 6.0 Test Chip at Intel Innovation 2023
See the Synopsys IP for PCIe 6.0 & Intel's PCIe 6.0-enabled test chip successful interop, a milestone for PCIe tech. The demo showcases link robustness @ 64GT/s and multiple speed changes using Synopsys & Intel HW and a Teledyne LeCroy Summit M616.
What’s New with Non-Volatile Memory (NVM) IP?
Understand the market changes driving NVM IP development, how the global wafer shortage is affecting NVM IP selection, and the latest development plans for Synopsys NVM IP.
AI SoC Chats: Understanding Compute Needs for AI SoCs
Will your next system require high performance AI? Learn what the latest systems are using for computation, including AI math, floating point and dot product hardware, and processor IP.
Meeting Cloud Data Bandwidth Requirements with HPC IP
As people continue to work remotely, demands on cloud data centers have never been higher. Chip designers for high-performance computing (HPC) SoCs are looking to new and innovative IP to meet their bandwidth, capacity, and security needs.
Silicon-Proven Automotive-Grade Synopsys IP
Get the latest on Synopsys' automotive IP portfolio supporting ISO 26262 functional safety, reliability, and quality management standards, with an available architecture for SoC development and safety management.
Broad Portfolio of IP for Mobile SoCs
Get the latest update on Synopsys IP for mobile SoCs, including MIPI C-PHY/D-PHY, USB 3.1, and UFS, which provide the necessary throughput, bandwidth, and efficiency for today’s advanced mobile SoCs.
Test & Repair Requirements for Autonomous Vehicles
Learn how advanced automotive semiconductors are being driven by ADAS & autonomous driving systems to move to smaller nodes. The presentation covers test & repair req's and solutions to help ensure automotive functional safety.
IP for Machine Learning Applications
The state of the art machine learning SoC performing facial recognition, natural language processing and social network filtering functions is causing innovations in IP, memory, semiconductor technology and packaging. Watch this video to learn about such innovations and machine learning SoCs’ unique design requirements.
What is ASIP Designer?
See how Synopsys’ ASIP Designer tool suite uses a single input specification to generate an SDK featuring a highly optimizing C compiler, instruction-set simulator, assembler, linker & debugger, and synthesizable RTL. The architectural exploration capability and the ability to make rapid changes in the processor model make it easy to optimize the processor for your requirements.